rv32g-core

commit 005a8afbb9eeaa3bda780697485b6b8b244102c3
parent f3051150934a71265497e9b012df43c53349aca4
Author: Vineet Kumar <git@vineetk.net>
Date:   Fri, 29 May 2026 02:07:52 -0400

add fetching support but needs tests

Diffstat:
M
rtl/rv32g_hart.sv
 | 
29
+++++++++++++++++++++--------
A
rtl/stage_fetch.sv
 | 
10
++++++++++

2 files changed, 31 insertions(+), 8 deletions(-)
diff --git a/rtl/rv32g_hart.sv b/rtl/rv32g_hart.sv
@@ -4,6 +4,7 @@ module rv32g_hart
 
    output logic [31:0] imem_addr,
    input logic [31:0]  imem_data,
+   input logic	       imem_valid,
 
    output logic [31:0] dmem_addr,
    input logic [31:0]  dmem_data,
@@ -13,19 +14,31 @@ module rv32g_hart
    // x0 to x31
    logic [31:0][31:0] regfile;
    logic [31:0]	      pc;
+   logic [31:0]	      next_pc;
+   logic [31:0]	      inst;
+   logic	      ctrl;	// TODO change to struct
+   
+   assign regfile[0] = 'd0;
+   always_ff @(posedge clk or negedge rstN) begin
+     if (!rstN) regfile <= '0;
+   end
 
-   // x0 is hardwired to 0
-   always_comb regfile[0] = 'd0;
+   stage_fetch u_fetch(.pc, .imem_addr, .imem_data, .inst);
 
    always_ff @(posedge clk or negedge rstN) begin
-     if (!rstN);		// TODO handle reset stuff
+     if (!rstN) pc <= '0;
+     else if (imem_valid) pc <= next_pc;
      else begin
-       // TODO instruction fetch
-       // TODO instruction decode
-       // TODO execution
-       // TODO memory
-       // TODO register writeback
+       // TODO (pipeline) IF/ID stall. if no instruction, just wait?
      end
    end
 
+   // TODO stage_decode  u_decode(.*);
+   // TODO stage_execute u_execute(.*);
+   // TODO stage_mem     u_mem(.*);
+   // TODO stage_wb      u_wb(.*);
+
+   // TODO replace with mux handling jumping
+   assign next_pc = pc + 4;
+
 endmodule: rv32g_hart
diff --git a/rtl/stage_fetch.sv b/rtl/stage_fetch.sv
@@ -0,0 +1,10 @@
+module stage_fetch
+  (input logic [31:0]  pc,
+   input logic [31:0]  imem_data,
+   output logic [31:0] imem_addr,
+   output logic [31:0] inst);
+
+   assign imem_addr = pc;
+   assign inst = imem_data;
+
+endmodule: stage_fetch