commit 2bd38ff833475a49673216b0d9f9f12d0bb643d6
parent bc1680a2ed231c8b186acc46d958d8e0c0090833
Author: Vineet Kumar <git@vineetk.net>
Date: Mon, 1 Jun 2026 22:57:58 -0400
move remaining decode typedefs to pkg for easier debugging access later
Diffstat:
| M | rtl/rv32g_pkg.sv | | | 89 | +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
| M | rtl/stage_decode.sv | | | 89 | ------------------------------------------------------------------------------- |
2 files changed, 89 insertions(+), 89 deletions(-)
diff --git a/rtl/rv32g_pkg.sv b/rtl/rv32g_pkg.sv
@@ -1,6 +1,95 @@
package rv32g_pkg;
typedef logic [31:0] reg_t;
+ typedef enum logic [3:0] {INVALIDTYPE,
+ RTYPE,
+ ITYPE,
+ STYPE,
+ BTYPE,
+ UTYPE,
+ JTYPE}
+ inst_type_t;
+
+ typedef enum {NAME_INVALID,
+ // rv32i
+ LUI,
+ AUIPC,
+ JAL,
+ JALR,
+ BEQ,
+ BNE,
+ BLT,
+ BGE,
+ BLTU,
+ BGEU,
+ LB,
+ LH,
+ LW,
+ LBU,
+ LHU,
+ SB,
+ SH,
+ SW,
+ ADDI,
+ SLTI,
+ SLTIU,
+ XORI,
+ ORI,
+ ANDI,
+ SLLI,
+ SRLI,
+ SRAI,
+ ADD,
+ SUB,
+ SLL,
+ SLT,
+ SLTU,
+ XOR,
+ SRL,
+ SRA,
+ OR,
+ AND,
+ FENCE,
+ FENCE_TSO,
+ PAUSE,
+ ECALL,
+ EBREAK}
+ inst_name_t;
+
+ // based off of Unprivileged ISA Chapter 36 Table 72 (no reserved)
+ typedef enum logic [6:0] {OPCODE_INVALID = 'b0000000,
+ // rv32i/m
+ OPCODE_LUI = 'b0110111,
+ OPCODE_AUIPC = 'b0010111,
+ OPCODE_JAL = 'b1101111,
+ OPCODE_JALR = 'b1100111,
+ OPCODE_BRANCH = 'b1100011,
+ OPCODE_LOAD = 'b0000011,
+ OPCODE_STORE = 'b0100011,
+ OPCODE_OP_IMM = 'b0010011,
+ OPCODE_OP = 'b0110011,
+ OPCODE_MISC_MEM = 'b0001111,
+ OPCODE_SYSTEM = 'b1110011,
+ // rv32f/d
+ OPCODE_LOAD_FP = 'b0000111,
+ OPCODE_STORE_FP = 'b0100111,
+ OPCODE_OP_FP = 'b1010011,
+ OPCODE_MADD = 'b1000011,
+ OPCODE_MSUB = 'b1000111,
+ OPCODE_NMADD = 'b1001111,
+ OPCODE_NMSUB = 'b1001011,
+ // rv32a
+ OPCODE_AMO = 'b0101111,
+ // rv32v
+ OPCODE_OP_V = 'b1010111,
+ OPCODE_OP_VE = 'b1110111,
+ // custom
+ OPCODE_CUSTOM_0 = 'b0001011,
+ OPCODE_CUSTOM_1 = 'b0101011,
+ OPCODE_CUSTOM_2 = 'b1011011,
+ OPCODE_CUSTOM_3 = 'b1111011}
+ opcode_t;
+
typedef enum logic [3:0] {// rv32i
ALU_NONE,
ALU_ADD,
diff --git a/rtl/stage_decode.sv b/rtl/stage_decode.sv
@@ -8,95 +8,6 @@ module stage_decode
output logic [31:0] rs2_val,
output logic [4:0] rd_num);
- typedef enum logic [3:0] {INVALIDTYPE,
- RTYPE,
- ITYPE,
- STYPE,
- BTYPE,
- UTYPE,
- JTYPE}
- inst_type_t;
-
- typedef enum {NAME_INVALID,
- // rv32i
- LUI,
- AUIPC,
- JAL,
- JALR,
- BEQ,
- BNE,
- BLT,
- BGE,
- BLTU,
- BGEU,
- LB,
- LH,
- LW,
- LBU,
- LHU,
- SB,
- SH,
- SW,
- ADDI,
- SLTI,
- SLTIU,
- XORI,
- ORI,
- ANDI,
- SLLI,
- SRLI,
- SRAI,
- ADD,
- SUB,
- SLL,
- SLT,
- SLTU,
- XOR,
- SRL,
- SRA,
- OR,
- AND,
- FENCE,
- FENCE_TSO,
- PAUSE,
- ECALL,
- EBREAK}
- inst_name_t;
-
- // based off of Unprivileged ISA Chapter 36 Table 72 (no reserved)
- typedef enum logic [6:0] {OPCODE_INVALID = 'b0000000,
- // rv32i/m
- OPCODE_LUI = 'b0110111,
- OPCODE_AUIPC = 'b0010111,
- OPCODE_JAL = 'b1101111,
- OPCODE_JALR = 'b1100111,
- OPCODE_BRANCH = 'b1100011,
- OPCODE_LOAD = 'b0000011,
- OPCODE_STORE = 'b0100011,
- OPCODE_OP_IMM = 'b0010011,
- OPCODE_OP = 'b0110011,
- OPCODE_MISC_MEM = 'b0001111,
- OPCODE_SYSTEM = 'b1110011,
- // rv32f/d
- OPCODE_LOAD_FP = 'b0000111,
- OPCODE_STORE_FP = 'b0100111,
- OPCODE_OP_FP = 'b1010011,
- OPCODE_MADD = 'b1000011,
- OPCODE_MSUB = 'b1000111,
- OPCODE_NMADD = 'b1001111,
- OPCODE_NMSUB = 'b1001011,
- // rv32a
- OPCODE_AMO = 'b0101111,
- // rv32v
- OPCODE_OP_V = 'b1010111,
- OPCODE_OP_VE = 'b1110111,
- // custom
- OPCODE_CUSTOM_0 = 'b0001011,
- OPCODE_CUSTOM_1 = 'b0101011,
- OPCODE_CUSTOM_2 = 'b1011011,
- OPCODE_CUSTOM_3 = 'b1111011}
- opcode_t;
-
logic [6:0] funct7 = inst[31:25];
logic [4:0] rs2_num = inst[24:20];
logic [4:0] rs1_num = inst[19:15];
