rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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commit 0b72748e55a5126780ae81c30ef9b3509c54ff93
parent 4c660e7b7a14192c296f37bb5fab00f011e1d559
Author: Vineet Kumar <git@vineetk.net>
Date:   Thu,  6 Aug 2026 18:55:45 +0530

remove the unused result address from test cases

just printing the register directly like I'm doing right now is easier
while in simulation.

Diffstat:
Mtests/riscv-tests/riscv_test.h | 10----------
1 file changed, 0 insertions(+), 10 deletions(-)

diff --git a/tests/riscv-tests/riscv_test.h b/tests/riscv-tests/riscv_test.h @@ -7,8 +7,6 @@ // Begin Macro //----------------------------------------------------------------------- -#define RESULT_ADDR 0x80004ffc - #define RVTEST_RV32U \ .macro init; \ .endm @@ -84,20 +82,12 @@ _start: \ #define RVTEST_PASS \ fence; \ -1: li TESTNUM, 1; \ - li x31, RESULT_ADDR; \ - sw TESTNUM, 0(x31); \ ecall; #define TESTNUM gp #define RVTEST_FAIL \ fence; \ -1: beqz TESTNUM, 1b; \ - addi x30, TESTNUM, 0; \ - slli x30, x30, 1; \ - ori x30, x30, 1; \ - sw x30, 0(x31); \ ebreak; //-----------------------------------------------------------------------