rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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commit 4c660e7b7a14192c296f37bb5fab00f011e1d559
parent 496803058d353510bac07fdb87673442e4298934
Author: Vineet Kumar <git@vineetk.net>
Date:   Wed,  5 Aug 2026 14:42:55 +0530

print the unmodified failed test number

Diffstat:
MMakefile | 7+++++--
Mtests/riscv-tests/riscv_test.h | 9+++++----
2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/Makefile b/Makefile @@ -14,7 +14,7 @@ NEXTPNR_DEV := GW5AST-LV138PG484AC1/I0 TEST_DIR := tests SIM := $(OBJDIR)/Vtb_rv32g CROSS_COMPILE := riscv32-unknown-elf- -CFLAGS := -static -fvisibility=hidden -nostdlib -nostartfiles -mabi=ilp32 +CFLAGS := -O0 -static -fvisibility=hidden -nostdlib -nostartfiles -mabi=ilp32 CPPFLAGS := -I. LDFLAGS := -Tlink.ld @@ -97,7 +97,10 @@ tests: tests-riscv-tests # clean clean-tests: - $(RM) $(TEST_DIR)/*.hex $(TEST_DIR)/*.pass $(TEST_DIR)/*.log $(TEST_LIST) + find $(TEST_DIR) -type f -name '*.dump' -exec $(RM) {} \; + find $(TEST_DIR) -type f -name '*.hex' -exec $(RM) {} \; + find $(TEST_DIR) -type f -name '*.log' -exec $(RM) {} \; + find $(TEST_DIR) -type f -executable -exec $(RM) {} \; clean: rm -rf $(OBJDIR) diff --git a/tests/riscv-tests/riscv_test.h b/tests/riscv-tests/riscv_test.h @@ -94,10 +94,11 @@ _start: \ #define RVTEST_FAIL \ fence; \ 1: beqz TESTNUM, 1b; \ - slli TESTNUM, TESTNUM, 1; \ - ori TESTNUM, TESTNUM, 1; \ - sw TESTNUM, 0(x31); \ - ebreak + addi x30, TESTNUM, 0; \ + slli x30, x30, 1; \ + ori x30, x30, 1; \ + sw x30, 0(x31); \ + ebreak; //----------------------------------------------------------------------- // Data Section Macro