commit 0ebcccf55db0716499c5c2f259694a3544d773b7 parent 6d2ce6f3c127bac56ba7f49f15cfe7049f2626f1 Author: Vineet Kumar <git@vineetk.net> Date: Tue, 9 Jun 2026 00:29:45 -0400 update makefile Diffstat:
| M | Makefile | | | 20 | ++++++++++++++++++-- |
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/Makefile b/Makefile @@ -3,7 +3,7 @@ OBJDIR := obj_dir PKG_SRC := ${SRCDIR}/rv32g_pkg.sv TB_SRC := ${SRCDIR}/tb_rv32g.sv -SV_SRCS := ${SRCDIR}/rv32g_hart.sv ${wildcard ${SRCDIR}/stage_*.sv} +SV_SRCS := ${SRCDIR}/rv32g_hart.sv ${wildcard ${SRCDIR}/stage_*.sv} ${SRCDIR}/unified_memory.sv all: lint synth @@ -16,13 +16,29 @@ lint: ${PKG_SRC} ${SV_SRCS} synth: yosys -m slang -p 'read_slang ${PKG_SRC} ${SV_SRCS}; synth_gowin -top rv32g_hart' -sim: lint ${PKG_SRC} ${TB_SRC} ${SV_SRCS} +sim_compile: lint ${PKG_SRC} ${TB_SRC} ${SV_SRCS} verilator --binary --exe --build --timing \ --top tb_rv32g \ -j 0 -o Vtb_rv32g \ --trace-fst \ ${PKG_SRC} ${TB_SRC} ${SV_SRCS} + +sim: sim_compile ./${OBJDIR}/Vtb_rv32g +tests: sim_compile + cd tests/isa && \ + make XLEN=32 && \ + rm -f *.dump && \ + for i in rv32ui-*; do \ + riscv32-unknown-elf-objcopy -O binary $$i file.bin; \ + hexdump -v -e '1/4 "%08x\n"' file.bin >$$i.hex; \ + rm file.bin; \ + done && \ + for i in rv32ui-*.hex; do \ + echo $$i; \ + ../../${OBJDIR}/Vtb_rv32g $$i; \ + done + clean: rm -rf ${OBJDIR}