rv32g-core

commit 6d2ce6f3c127bac56ba7f49f15cfe7049f2626f1
parent 34a120d7b08431486d84157a8922e6856af50405
Author: Vineet Kumar <git@vineetk.net>
Date:   Mon,  8 Jun 2026 17:45:08 -0400

implement Zifencei as a nop

Diffstat:
M
rtl/rv32g_pkg.sv
 | 
1
+
M
rtl/stage_decode.sv
 | 
15
+++++++++++----

2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/rtl/rv32g_pkg.sv b/rtl/rv32g_pkg.sv
@@ -50,6 +50,7 @@ package rv32g_pkg;
 		 OR,
 		 AND,
 		 FENCE,
+		 FENCE_I,
 		 FENCE_TSO,
 		 PAUSE,
 		 ECALL,
diff --git a/rtl/stage_decode.sv b/rtl/stage_decode.sv
@@ -99,12 +99,12 @@ module stage_decode
        {7'b0000000, 3'b110, OPCODE_OP}: name = OR;
        {7'b0000000, 3'b111, OPCODE_OP}: name = AND;
        {7'b???????, 3'b000, OPCODE_MISC_MEM}: begin
-	 // FENCE{,.TSO}/PAUSE encoding is a bit different
-	 if (rs1_num == '0) begin
+	 // FENCE{,.I,.TSO}/PAUSE encoding is a bit different
+	 if (rs1_num == '0 && rd_num == '0) begin
 	   if (inst[31:20] == 'b1000_0011_0011) name = FENCE_TSO;
 	   else if (inst[31:20] == 'b0000_0001_0000) name = PAUSE;
-	   else name = NAME_INVALID;
-	 end else name = FENCE;
+	   else name = FENCE;
+	 end else name = NAME_INVALID;
        end
        {7'b0000000, 3'b000, OPCODE_SYSTEM}: begin
 	 // ECALL and EBREAK encoding is also a bit different
@@ -112,6 +112,11 @@ module stage_decode
 	   name = (rs2_num[0] == '0) ? ECALL : EBREAK;
 	 end else name = NAME_INVALID;
        end
+       // Zifencei
+       {7'b0000000, 3'b001, OPCODE_MISC_MEM}: begin
+	 if (rs1_num == '0 && rd_num == '0 && inst[31:20] == '0) name = FENCE_I;
+	 else name = NAME_INVALID;
+       end
        default: name = NAME_INVALID;
      endcase
    end
@@ -251,6 +256,8 @@ module stage_decode
        // SYSTEM instructions do traps
        ECALL: ctrl.exception = EXC_CALL;
        EBREAK: ctrl.exception = EXC_BKPT;
+       // Zifencei
+       FENCE_I: ;
        default: ctrl.exception = EXC_ILL_INST;
      endcase
    end