rv32g-core

commit 22609eac8bfa675d069b1967f8c6fef7f5ea1d28
parent 515c289c366231ce253950a2774c15eebc7bc379
Author: Vineet Kumar <git@vineetk.net>
Date:   Mon,  1 Jun 2026 21:19:14 -0400

add writeback stage

Diffstat:
M
rtl/rv32g_hart.sv
 | 
3
++-
A
rtl/stage_writeback.sv
 | 
27
+++++++++++++++++++++++++++

2 files changed, 29 insertions(+), 1 deletion(-)
diff --git a/rtl/rv32g_hart.sv b/rtl/rv32g_hart.sv
@@ -64,7 +64,8 @@ module rv32g_hart
    // TODO MEM/WB pipeline register
    // TODO find out what else needs to be done in between stages
 
-   // TODO stage_wb u_wb(.ctrl, .alu_out, .rd_num, .regfile);
+   stage_writeback u_wb(.clk, .rstN, .wbsrc(ctrl.wbsrc), .rd_num, .regfile,
+			.pc, .imm, .alu_out, .mem_out);
    // TODO find out what else needs to be done after this stage
 
    always_comb begin
diff --git a/rtl/stage_writeback.sv b/rtl/stage_writeback.sv
@@ -0,0 +1,27 @@
+module stage_writeback
+  import rv32g_pkg::*;
+   (input logic	      clk,
+    input logic	      rstN,
+    input wbsrc_t     wbsrc,
+    input logic [4:0] rd_num,
+    input reg_t	      pc,
+    input reg_t	      imm,
+    input reg_t	      alu_out,
+    input reg_t	      mem_out,
+    output reg_t      regfile [0:31]);
+
+   always_ff @(posedge clk or negedge rstN) begin
+     if (!rstN) begin
+       for (int i = 0; i < 32; i++) regfile[i] <= '0;
+     end else if (rd_num != 0) begin
+       unique case (wbsrc)
+	 WB_NONE: ;
+	 WB_PC: regfile[rd_num] <= pc + 4;
+	 WB_ALU: regfile[rd_num] <= alu_out;
+	 WB_MEM: regfile[rd_num] <= mem_out;
+	 WB_IMM: regfile[rd_num] <= imm;
+       endcase
+     end
+   end
+
+endmodule