rv32g-core

commit bc1680a2ed231c8b186acc46d958d8e0c0090833
parent 22609eac8bfa675d069b1967f8c6fef7f5ea1d28
Author: Vineet Kumar <git@vineetk.net>
Date:   Mon,  1 Jun 2026 22:57:39 -0400

add stubs for unused signals in hart's top-level

Diffstat:
M
rtl/rv32g_hart.sv
 | 
17
++++++++++++++++-

1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/rtl/rv32g_hart.sv b/rtl/rv32g_hart.sv
@@ -29,7 +29,6 @@ module rv32g_hart
    reg_t	mem_out;
    logic	branch_taken;
    
-   assign regfile[0] = 'd0;
    always_ff @(posedge clk or negedge rstN) begin
      if (!rstN) begin
        for (int i = 0; i < 32; i++) regfile[i] <= '0;
@@ -48,6 +47,18 @@ module rv32g_hart
 
    stage_decode u_decode(.inst, .regfile, .ctrl, .imm, .rs1_val, .rs2_val, .rd_num);
    // TODO ID/EX pipeline register
+   always_ff @(posedge clk or negedge rstN) begin
+     if (!rstN) ; // TODO reset pipeline register
+     else if (ctrl.exception != EXC_NONE) begin
+       // TODO handle exceptions
+       unique case (ctrl.exception)
+	 EXC_NONE: ;
+	 EXC_ILL_INST: ;
+	 EXC_CALL: ;
+	 EXC_BKPT: ;
+       endcase
+     end
+   end
    // TODO find out what else needs to be done in between stages like exceptions
 
    stage_execute u_execute(.op(ctrl.aluop),
@@ -57,6 +68,10 @@ module rv32g_hart
 			   .out(alu_out),
 			   .imm, .pc, .rs1_val, .rs2_val, .branch_taken);
    // TODO EX/MEM pipeline register
+   always_ff @(posedge clk or negedge rstN) begin
+     if (!rstN) ; // TODO reset pipeline register
+     else if (!dmem_valid && ctrl.memop != MEM_NONE) ; // TODO stall
+   end
    // TODO stall when dmem_valid is 0 and ctrl.memop != 0. find out what else needs to be done in between stages
    
    stage_memory u_mem(.memop(ctrl.memop), .alu_out, .rs2_val,