rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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commit 34a120d7b08431486d84157a8922e6856af50405
parent 32fe040d304c97cd13c82b9cd44e1fe5a0082245
Author: Vineet Kumar <git@vineetk.net>
Date:   Mon,  8 Jun 2026 17:40:34 -0400

add rv32 toolchain to manifest.scm

Diffstat:
Mmanifest.scm | 4+++-
1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/manifest.scm b/manifest.scm @@ -1,5 +1,6 @@ (use-modules (gnu packages base) (gnu packages commencement) + (gnu packages cross-base) (gnu packages electronics) (gnu packages python)) @@ -7,4 +8,5 @@ gnu-make python verilator - yosys)) + yosys + (cross-gcc-toolchain "riscv32-unknown-elf")))