rv32g-core

commit 496803058d353510bac07fdb87673442e4298934
parent 7dc30f86975ae4540c0449692d7efb4ef62005a3
Author: Vineet Kumar <git@vineetk.net>
Date:   Wed,  5 Aug 2026 14:42:41 +0530

test only for rv32ui right now

Diffstat:
M
Makefile
 | 
3
++-

1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Makefile b/Makefile
@@ -81,8 +81,9 @@ tests-riscv-tests_compile: # crazy name
 	done
 
 tests-riscv-tests: sim_compile tests-riscv-tests_compile
+#	for i in rv32*/*.hex; do
 	@cd $(TEST_DIR)/riscv-tests && \
-	for i in rv32*/*.hex; do \
+	for i in rv32ui/*.hex; do \
 	    ../../$(SIM) +rom="$$i" 2>&1 | tee "$${i%%.hex}.log" | grep -E 'pass|fail'; \
 	done; \
 	grep -ohE 'pass|fail' rv32*/*.log | sort | uniq -c