commit 7dc30f86975ae4540c0449692d7efb4ef62005a3
parent fe9f4859cde2e57a482a8af26275e659bcf6f6c7
Author: Vineet Kumar <git@vineetk.net>
Date: Tue, 4 Aug 2026 18:12:36 +0530
fix test running and remove rv64-specific tests
Diffstat:
36 files changed, 87 insertions(+), 1862 deletions(-)
diff --git a/.gitignore b/.gitignore
@@ -4,5 +4,8 @@ tests/.test_list
design.json
design_pnr.json
*.rpt
+*.hex
+*.log
+*.dump
runs/
rom.txt
diff --git a/Makefile b/Makefile
@@ -11,11 +11,12 @@ CST_SRC := ${SRCDIR}/rv32g_hart_top.cst
NEXTPNR_DEV := GW5AST-LV138PG484AC1/I0
# tests
-TEST_DIR := tests/riscv-tests/isa
-SIM := $(OBJDIR)/Vtb_rv32g
-ELF2HEX := tests/elf2hex
-LOG_DIR := $(TEST_DIR)/logs
-TEST_LIST := $(TEST_DIR)/test_list
+TEST_DIR := tests
+SIM := $(OBJDIR)/Vtb_rv32g
+CROSS_COMPILE := riscv32-unknown-elf-
+CFLAGS := -static -fvisibility=hidden -nostdlib -nostartfiles -mabi=ilp32
+CPPFLAGS := -I.
+LDFLAGS := -Tlink.ld
# main
.PHONY: all lint synth sim_compile sim tests clean clean-tests
@@ -46,42 +47,50 @@ sim: sim_compile
./$(SIM)
# tests
-$(TEST_DIR)/%.hex: $(TEST_DIR)/% | $(TEST_LIST)
- find ${TEST_DIR} -type f -executable -exec $(ELF2HEX) {} \;
-
-$(TEST_DIR)/%.pass: $(TEST_DIR)/%.hex sim_compile
- @mkdir -p $(LOG_DIR)
- @printf "%20s: " $(basename $(notdir $<))
- @pass=$$(readelf -s $(basename $<) | awk '/pass$$/ {print $$2}'); \
- fail=$$(readelf -s $(basename $<) | awk '/fail$$/ {print $$2}'); \
- $(SIM) +rom=$< > $(LOG_DIR)/$*.log; \
- if ! $$(readelf -s $(basename $<) | grep -qE 'pass|fail'); then \
- echo "pass and fail functions not found"; \
- elif grep -q "^IF: pc: $$fail" $(LOG_DIR)/$*.log; then \
- echo "fail"; \
- elif grep -q "^IF: pc: $$pass" $(LOG_DIR)/$*.log; then \
- echo "pass"; \
- else \
- echo "ERROR (neither pass nor fail address reached)"; \
- exit 1; \
- fi
- @touch $@
-
-$(TEST_LIST):
- @cd $(TEST_DIR) && \
- $(MAKE) -k XLEN=32 || true && \
- $(RM) *.dump && \
- names=$$(for f in rv32ui-*; do \
- [ -f "$$f" ] && [ ! "$$f" = "*.dump" ] && echo "$${f}"; \
- done | tr '\n' ' ') && \
- echo "TEST_NAMES := $$names" > $(notdir $@)
-
--include $(TEST_LIST)
-TEST_TARGETS := $(addprefix $(TEST_DIR)/,$(addsuffix .pass,$(TEST_NAMES)))
+tests-riscv-tests_compile: # crazy name
+ @cd "$(TEST_DIR)/riscv-tests" && \
+ for i in rv32ui/*.S; do \
+ $(CROSS_COMPILE)gcc $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) -march=rv32i_zifencei "$$i" -o tmp && \
+ $(CROSS_COMPILE)objdump -d tmp >"$${i%%.S}.dump" || exit 1; \
+ $(CROSS_COMPILE)objcopy -Overilog --verilog-data-width=4 tmp "$${i%%.S}.hex" || exit 1; \
+ rm -f tmp; \
+ done && \
+ for i in rv32um/*.S; do \
+ $(CROSS_COMPILE)gcc $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) -march=rv32im "$$i" -o tmp && \
+ $(CROSS_COMPILE)objdump -d tmp >"$${i%%.S}.dump" || exit 1; \
+ $(CROSS_COMPILE)objcopy -Overilog --verilog-data-width=4 tmp "$${i%%.S}.hex" || exit 1; \
+ rm -f tmp; \
+ done && \
+ for i in rv32ua/*.S; do \
+ $(CROSS_COMPILE)gcc $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) -march=rv32ia "$$i" -o tmp && \
+ $(CROSS_COMPILE)objdump -d tmp >"$${i%%.S}.dump" || exit 1; \
+ $(CROSS_COMPILE)objcopy -Overilog --verilog-data-width=4 tmp "$${i%%.S}.hex" || exit 1; \
+ rm -f tmp; \
+ done && \
+ for i in rv32uf/*.S; do \
+ $(CROSS_COMPILE)gcc $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) -march=rv32if "$$i" -o tmp && \
+ $(CROSS_COMPILE)objdump -d tmp >"$${i%%.S}.dump" || exit 1; \
+ $(CROSS_COMPILE)objcopy -Overilog --verilog-data-width=4 tmp "$${i%%.S}.hex" || exit 1; \
+ rm -f tmp; \
+ done && \
+ for i in rv32ud/*.S; do \
+ $(CROSS_COMPILE)gcc $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) -march=rv32g "$$i" -o tmp && \
+ $(CROSS_COMPILE)objdump -d tmp >"$${i%%.S}.dump" || exit 1; \
+ $(CROSS_COMPILE)objcopy -Overilog --verilog-data-width=4 tmp "$${i%%.S}.hex" || exit 1; \
+ rm -f tmp; \
+ done
+
+tests-riscv-tests: sim_compile tests-riscv-tests_compile
+ @cd $(TEST_DIR)/riscv-tests && \
+ for i in rv32*/*.hex; do \
+ ../../$(SIM) +rom="$$i" 2>&1 | tee "$${i%%.hex}.log" | grep -E 'pass|fail'; \
+ done; \
+ grep -ohE 'pass|fail' rv32*/*.log | sort | uniq -c
+# TODO do same for gh:riscv/riscv-arch-test
# build and run all tests
.PHONY: tests
-tests: $(TEST_LIST) $(TEST_TARGETS)
+tests: tests-riscv-tests
@echo ${TEST_LIST}
@echo "All tests ran."
diff --git a/rtl/tb_rv32g.sv b/rtl/tb_rv32g.sv
@@ -112,7 +112,7 @@ module tb_rv32g
$display("+++ %s: pass (%0d cycles) +++", rom_filename, cycle_cnt);
$finish();
end else if (exception == EXC_BKPT) begin
- $display("+++ %s: fail (test %0d, %0d cycles) +++", rom_filename, dut.regfile[3], cycle_cnt);
+ $display("--- %s: fail (test %0d, %0d cycles) ---", rom_filename, dut.regfile[3], cycle_cnt);
$finish();
end
diff --git a/tests/riscv-tests/riscv_test.h b/tests/riscv-tests/riscv_test.h
@@ -16,7 +16,6 @@
#define RVTEST_RV32UF \
.macro init; \
- RVTEST_FP_ENABLE; \
.endm
#define RVTEST_RV64UF RVTEST_RV32UF
#define TEST_FP_INT_OP_D TEST_FP_INT_OP_D32
diff --git a/tests/riscv-tests/rv32ua/amoadd_d.S b/tests/riscv-tests/rv32ua/amoadd_d.S
@@ -1,47 +0,0 @@
-# See LICENSE for license details.
-
-#*****************************************************************************
-# amoadd_d.S
-#-----------------------------------------------------------------------------
-#
-# Test amoadd.d instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0xffffffff80000000, \
- li a0, 0xffffffff80000000; \
- li a1, 0xfffffffffffff800; \
- la a3, amo_operand; \
- sd a0, 0(a3); \
- amoadd.d a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0xffffffff7ffff800, ld a5, 0(a3))
-
- # try again after a cache miss
- TEST_CASE(4, a4, 0xffffffff7ffff800, \
- amoadd.d a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 0xffffffff7ffff000, ld a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
-
- .bss
- .align 3
-amo_operand:
- .dword 0
diff --git a/tests/riscv-tests/rv32ua/amoand_d.S b/tests/riscv-tests/rv32ua/amoand_d.S
@@ -1,48 +0,0 @@
-# See LICENSE for license details.
-
-#*****************************************************************************
-# amoand_d.S
-#-----------------------------------------------------------------------------
-#
-# Test amoand.d instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0xffffffff80000000, \
- li a0, 0xffffffff80000000; \
- li a1, 0xfffffffffffff800; \
- la a3, amo_operand; \
- sd a0, 0(a3); \
- amoand.d a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3))
-
- # try again after a cache miss
- TEST_CASE(4, a4, 0xffffffff80000000, \
- li a1, 0x0000000080000000; \
- amoand.d a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 0x0000000080000000, ld a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
-
- .bss
- .align 3
-amo_operand:
- .dword 0
diff --git a/tests/riscv-tests/rv32ua/amomax_d.S b/tests/riscv-tests/rv32ua/amomax_d.S
@@ -1,48 +0,0 @@
-# See LICENSE for license details.
-
-#*****************************************************************************
-# amomax_d.S
-#-----------------------------------------------------------------------------
-#
-# Test amomax.d instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0xffffffff80000000, \
- li a0, 0xffffffff80000000; \
- li a1, 0xfffffffffffff800; \
- la a3, amo_operand; \
- sd a0, 0(a3); \
- amomax.d a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3))
-
- TEST_CASE(4, a4, 0, \
- li a1, 1; \
- sd x0, 0(a3); \
- amomax.d a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 1, ld a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
-
- .bss
- .align 3
-amo_operand:
- .dword 0
diff --git a/tests/riscv-tests/rv32ua/amomaxu_d.S b/tests/riscv-tests/rv32ua/amomaxu_d.S
@@ -1,48 +0,0 @@
-# See LICENSE for license details.
-
-#*****************************************************************************
-# amomaxu_d.S
-#-----------------------------------------------------------------------------
-#
-# Test amomaxu.d instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0xffffffff80000000, \
- li a0, 0xffffffff80000000; \
- li a1, 0xfffffffffffff800; \
- la a3, amo_operand; \
- sd a0, 0(a3); \
- amomaxu.d a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3))
-
- TEST_CASE(4, a4, 0, \
- li a1, 0xffffffffffffffff; \
- sd x0, 0(a3); \
- amomaxu.d a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 0xffffffffffffffff, ld a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
-
- .bss
- .align 3
-amo_operand:
- .dword 0
diff --git a/tests/riscv-tests/rv32ua/amomin_d.S b/tests/riscv-tests/rv32ua/amomin_d.S
@@ -1,48 +0,0 @@
-# See LICENSE for license details.
-
-#*****************************************************************************
-# amomin_d.S
-#-----------------------------------------------------------------------------
-#
-# Test amomin.d instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0xffffffff80000000, \
- li a0, 0xffffffff80000000; \
- li a1, 0xfffffffffffff800; \
- la a3, amo_operand; \
- sd a0, 0(a3); \
- amomin.d a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3))
-
- TEST_CASE(4, a4, 0, \
- li a1, 0xffffffffffffffff; \
- sd x0, 0(a3); \
- amomin.d a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 0xffffffffffffffff, ld a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
-
- .bss
- .align 3
-amo_operand:
- .dword 0
diff --git a/tests/riscv-tests/rv32ua/amominu_d.S b/tests/riscv-tests/rv32ua/amominu_d.S
@@ -1,49 +0,0 @@
-# See LICENSE for license details.
-
-#*****************************************************************************
-# amominu_d.S
-#-----------------------------------------------------------------------------
-#
-# Test amominu.d instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0xffffffff80000000, \
- li a0, 0xffffffff80000000; \
- li a1, 0xfffffffffffff800; \
- la a3, amo_operand; \
- sd a0, 0(a3); \
- amominu.d a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3))
-
- TEST_CASE(4, a4, 0, \
- li a1, 0xffffffffffffffff; \
- sd x0, 0(a3); \
- amominu.d a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 0, ld a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
-
- .bss
- .align 3
-amo_operand:
- .dword 0
-
diff --git a/tests/riscv-tests/rv32ua/amoor_d.S b/tests/riscv-tests/rv32ua/amoor_d.S
@@ -1,48 +0,0 @@
-# See LICENSE for license details.
-
-#*****************************************************************************
-# amoor_d.S
-#-----------------------------------------------------------------------------
-#
-# Test amoor.d instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0xffffffff80000000, \
- li a0, 0xffffffff80000000; \
- li a1, 0xfffffffffffff800; \
- la a3, amo_operand; \
- sd a0, 0(a3); \
- amoor.d a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3))
-
- # try again after a cache miss
- TEST_CASE(4, a4, 0xfffffffffffff800, \
- li a1, 1; \
- amoor.d a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 0xfffffffffffff801, ld a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
-
- .bss
- .align 3
-amo_operand:
- .dword 0
diff --git a/tests/riscv-tests/rv32ua/amoswap_d.S b/tests/riscv-tests/rv32ua/amoswap_d.S
@@ -1,48 +0,0 @@
-# See LICENSE for license details.
-
-#*****************************************************************************
-# amoswap.d.S
-#-----------------------------------------------------------------------------
-#
-# Test amoswap.d instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0xffffffff80000000, \
- li a0, 0xffffffff80000000; \
- li a1, 0xfffffffffffff800; \
- la a3, amo_operand; \
- sd a0, 0(a3); \
- amoswap.d a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3))
-
- # try again after a cache miss
- TEST_CASE(4, a4, 0xfffffffffffff800, \
- li a1, 0x0000000080000000; \
- amoswap.d a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 0x0000000080000000, ld a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
-
- .bss
- .align 3
-amo_operand:
- .dword 0
diff --git a/tests/riscv-tests/rv32ua/amoxor_d.S b/tests/riscv-tests/rv32ua/amoxor_d.S
@@ -1,48 +0,0 @@
-# See LICENSE for license details.
-
-#*****************************************************************************
-# amoxor_d.S
-#-----------------------------------------------------------------------------
-#
-# Test amoxor.d instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0xffffffff80000000, \
- li a0, 0xffffffff80000000; \
- li a1, 0xfffffffffffff800; \
- la a3, amo_operand; \
- sd a0, 0(a3); \
- amoxor.d a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0x000000007ffff800, ld a5, 0(a3))
-
- # try again after a cache miss
- TEST_CASE(4, a4, 0x000000007ffff800, \
- li a1, 1; \
- amoxor.d a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 0x000000007ffff801, ld a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
-
- .bss
- .align 3
-amo_operand:
- .dword 0
diff --git a/tests/riscv-tests/rv32ud/fadd.S b/tests/riscv-tests/rv32ud/fadd.S
@@ -13,13 +13,11 @@
RVTEST_RV64UF
RVTEST_CODE_BEGIN
-#if __riscv_xlen == 32
- # Replace the function with the 32-bit variant defined in test_macros.h
- #undef TEST_FP_OP2_D
- #define TEST_FP_OP2_D TEST_FP_OP2_D32
- #undef TEST_FP_OP2_D_HEX
- #define TEST_FP_OP2_D_HEX TEST_FP_OP2_D32_HEX
-#endif
+ # Replace the function with the 32-bit variant defined in test_macros.h
+ #undef TEST_FP_OP2_D
+ #define TEST_FP_OP2_D TEST_FP_OP2_D32
+ #undef TEST_FP_OP2_D_HEX
+ #define TEST_FP_OP2_D_HEX TEST_FP_OP2_D32_HEX
#-------------------------------------------------------------
# Arithmetic tests
diff --git a/tests/riscv-tests/rv32ud/fclass.S b/tests/riscv-tests/rv32ud/fclass.S
@@ -13,11 +13,9 @@
RVTEST_RV64UF
RVTEST_CODE_BEGIN
-#if __riscv_xlen == 32
- # Replace the function with the 32-bit variant defined in test_macros.h
- #undef TEST_FCLASS_D
- #define TEST_FCLASS_D TEST_FCLASS_D32
-#endif
+ # Replace the function with the 32-bit variant defined in test_macros.h
+ #undef TEST_FCLASS_D
+ #define TEST_FCLASS_D TEST_FCLASS_D32
#-------------------------------------------------------------
# Arithmetic tests
diff --git a/tests/riscv-tests/rv32ud/fcmp.S b/tests/riscv-tests/rv32ud/fcmp.S
@@ -17,13 +17,11 @@ RVTEST_CODE_BEGIN
# Arithmetic tests
#-------------------------------------------------------------
-#if __riscv_xlen == 32
- # Replace the function with the 32-bit variant defined in test_macros.h
- #undef TEST_FP_CMP_OP_D
- #define TEST_FP_CMP_OP_D TEST_FP_CMP_OP_D32
- #undef TEST_FP_CMP_OP_D_HEX
- #define TEST_FP_CMP_OP_D_HEX TEST_FP_CMP_OP_D32_HEX
-#endif
+ # Replace the function with the 32-bit variant defined in test_macros.h
+ #undef TEST_FP_CMP_OP_D
+ #define TEST_FP_CMP_OP_D TEST_FP_CMP_OP_D32
+ #undef TEST_FP_CMP_OP_D_HEX
+ #define TEST_FP_CMP_OP_D_HEX TEST_FP_CMP_OP_D32_HEX
TEST_FP_CMP_OP_D( 2, feq.d, 0x00, 1, -1.36, -1.36)
TEST_FP_CMP_OP_D( 3, fle.d, 0x00, 1, -1.36, -1.36)
diff --git a/tests/riscv-tests/rv32ud/fcvt.S b/tests/riscv-tests/rv32ud/fcvt.S
@@ -13,14 +13,12 @@
RVTEST_RV64UF
RVTEST_CODE_BEGIN
-#if __riscv_xlen == 32
- # Replace the function with the 32-bit variant defined in test_macros.h
- #undef TEST_INT_FP_OP_D
- #define TEST_INT_FP_OP_D TEST_INT_FP_OP_D32
+ # Replace the function with the 32-bit variant defined in test_macros.h
+ #undef TEST_INT_FP_OP_D
+ #define TEST_INT_FP_OP_D TEST_INT_FP_OP_D32
- #undef TEST_FCVT_S_D
- #define TEST_FCVT_S_D TEST_FCVT_S_D32
-#endif
+ #undef TEST_FCVT_S_D
+ #define TEST_FCVT_S_D TEST_FCVT_S_D32
#-------------------------------------------------------------
# Arithmetic tests
@@ -32,27 +30,9 @@ RVTEST_CODE_BEGIN
TEST_INT_FP_OP_D(4, fcvt.d.wu, 2.0, 2);
TEST_INT_FP_OP_D(5, fcvt.d.wu, 4294967294, -2);
-#if __riscv_xlen >= 64
- TEST_INT_FP_OP_D(6, fcvt.d.l, 2.0, 2);
- TEST_INT_FP_OP_D(7, fcvt.d.l, -2.0, -2);
-
- TEST_INT_FP_OP_D(8, fcvt.d.lu, 2.0, 2);
- TEST_INT_FP_OP_D(9, fcvt.d.lu, 1.8446744073709552e19, -2);
-#endif
-
TEST_FCVT_S_D(10, -1.5, -1.5)
TEST_FCVT_D_S(11, -1.5, -1.5)
-#if __riscv_xlen >= 64
- TEST_CASE(12, a0, qNaNd,
- la a1, test_data_22;
- ld a2, 0(a1);
- fmv.d.x f2, a2;
- fcvt.s.d f2, f2;
- fcvt.d.s f2, f2;
- fmv.x.d a0, f2;
- )
-#else
TEST_CASE_D32(12, a0, a1, qNaNd,
la a1, test_data_22;
fld f2, 0(a1);
@@ -62,7 +42,6 @@ RVTEST_CODE_BEGIN
lw a0, 0(a1);
lw a1, 4(a1)
)
-#endif
TEST_PASSFAIL
diff --git a/tests/riscv-tests/rv32ud/fcvt_w.S b/tests/riscv-tests/rv32ud/fcvt_w.S
@@ -1,114 +0,0 @@
-# See LICENSE for license details.
-
-#*****************************************************************************
-# fcvt_w.S
-#-----------------------------------------------------------------------------
-#
-# Test fcvt{wu|w|lu|l}.d instructions.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64UF
-RVTEST_CODE_BEGIN
-
- #-------------------------------------------------------------
- # Arithmetic tests
- #-------------------------------------------------------------
-
- TEST_FP_INT_OP_D( 2, fcvt.w.d, 0x01, -1, -1.1, rtz);
- TEST_FP_INT_OP_D( 3, fcvt.w.d, 0x00, -1, -1.0, rtz);
- TEST_FP_INT_OP_D( 4, fcvt.w.d, 0x01, 0, -0.9, rtz);
- TEST_FP_INT_OP_D( 5, fcvt.w.d, 0x01, 0, 0.9, rtz);
- TEST_FP_INT_OP_D( 6, fcvt.w.d, 0x00, 1, 1.0, rtz);
- TEST_FP_INT_OP_D( 7, fcvt.w.d, 0x01, 1, 1.1, rtz);
- TEST_FP_INT_OP_D( 8, fcvt.w.d, 0x10, -1<<31, -3e9, rtz);
- TEST_FP_INT_OP_D( 9, fcvt.w.d, 0x10, (1<<31)-1, 3e9, rtz);
-
- TEST_FP_INT_OP_D(12, fcvt.wu.d, 0x10, 0, -3.0, rtz);
- TEST_FP_INT_OP_D(13, fcvt.wu.d, 0x10, 0, -1.0, rtz);
- TEST_FP_INT_OP_D(14, fcvt.wu.d, 0x01, 0, -0.9, rtz);
- TEST_FP_INT_OP_D(15, fcvt.wu.d, 0x01, 0, 0.9, rtz);
- TEST_FP_INT_OP_D(16, fcvt.wu.d, 0x00, 1, 1.0, rtz);
- TEST_FP_INT_OP_D(17, fcvt.wu.d, 0x01, 1, 1.1, rtz);
- TEST_FP_INT_OP_D(18, fcvt.wu.d, 0x10, 0, -3e9, rtz);
- TEST_FP_INT_OP_D(19, fcvt.wu.d, 0x00, 0xffffffffb2d05e00, 3e9, rtz);
-
-#if __riscv_xlen >= 64
- TEST_FP_INT_OP_D(22, fcvt.l.d, 0x01, -1, -1.1, rtz);
- TEST_FP_INT_OP_D(23, fcvt.l.d, 0x00, -1, -1.0, rtz);
- TEST_FP_INT_OP_D(24, fcvt.l.d, 0x01, 0, -0.9, rtz);
- TEST_FP_INT_OP_D(25, fcvt.l.d, 0x01, 0, 0.9, rtz);
- TEST_FP_INT_OP_D(26, fcvt.l.d, 0x00, 1, 1.0, rtz);
- TEST_FP_INT_OP_D(27, fcvt.l.d, 0x01, 1, 1.1, rtz);
- TEST_FP_INT_OP_D(28, fcvt.l.d, 0x00,-3000000000, -3e9, rtz);
- TEST_FP_INT_OP_D(29, fcvt.l.d, 0x00, 3000000000, 3e9, rtz);
- TEST_FP_INT_OP_D(20, fcvt.l.d, 0x10, -1<<63,-3e19, rtz);
- TEST_FP_INT_OP_D(21, fcvt.l.d, 0x10, (1<<63)-1, 3e19, rtz);
-
- TEST_FP_INT_OP_D(32, fcvt.lu.d, 0x10, 0, -3.0, rtz);
- TEST_FP_INT_OP_D(33, fcvt.lu.d, 0x10, 0, -1.0, rtz);
- TEST_FP_INT_OP_D(34, fcvt.lu.d, 0x01, 0, -0.9, rtz);
- TEST_FP_INT_OP_D(35, fcvt.lu.d, 0x01, 0, 0.9, rtz);
- TEST_FP_INT_OP_D(36, fcvt.lu.d, 0x00, 1, 1.0, rtz);
- TEST_FP_INT_OP_D(37, fcvt.lu.d, 0x01, 1, 1.1, rtz);
- TEST_FP_INT_OP_D(38, fcvt.lu.d, 0x10, 0, -3e9, rtz);
- TEST_FP_INT_OP_D(39, fcvt.lu.d, 0x00, 3000000000, 3e9, rtz);
-#endif
-
- # test negative NaN, negative infinity conversion
- TEST_CASE(42, x1, 0x000000007fffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.w.d x1, f1)
-#if __riscv_xlen >= 64
- TEST_CASE(43, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.l.d x1, f1)
-#endif
- TEST_CASE(44, x1, 0xffffffff80000000, la x1, tdat_d; fld f1, 16(x1); fcvt.w.d x1, f1)
-#if __riscv_xlen >= 64
- TEST_CASE(45, x1, 0x8000000000000000, la x1, tdat_d; fld f1, 16(x1); fcvt.l.d x1, f1)
-#endif
-
- # test positive NaN, positive infinity conversion
- TEST_CASE(52, x1, 0x000000007fffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.w.d x1, f1)
-#if __riscv_xlen >= 64
- TEST_CASE(53, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.l.d x1, f1)
-#endif
- TEST_CASE(54, x1, 0x000000007fffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.w.d x1, f1)
-#if __riscv_xlen >= 64
- TEST_CASE(55, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.l.d x1, f1)
-#endif
-
- # test NaN, infinity conversions to unsigned integer
- TEST_CASE(62, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.wu.d x1, f1)
- TEST_CASE(63, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.wu.d x1, f1)
- TEST_CASE(64, x1, 0, la x1, tdat_d; fld f1, 16(x1); fcvt.wu.d x1, f1)
- TEST_CASE(65, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.wu.d x1, f1)
-#if __riscv_xlen >= 64
- TEST_CASE(66, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.lu.d x1, f1)
- TEST_CASE(67, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.lu.d x1, f1)
- TEST_CASE(68, x1, 0, la x1, tdat_d; fld f1, 16(x1); fcvt.lu.d x1, f1)
- TEST_CASE(69, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.lu.d x1, f1)
-#endif
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-# -NaN, NaN, -inf, +inf
-tdat:
-.word 0xffffffff
-.word 0x7fffffff
-.word nInff
-.word Inff
-
-tdat_d:
-.dword 0xffffffffffffffff
-.dword 0x7fffffffffffffff
-.dword nInfd
-.dword Infd
-
-RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ud/fdiv.S b/tests/riscv-tests/rv32ud/fdiv.S
@@ -13,17 +13,15 @@
RVTEST_RV64UF
RVTEST_CODE_BEGIN
-#if __riscv_xlen == 32
- # Replace the functions with the 32-bit variants defined in test_macros.h
- #undef TEST_FP_OP2_D
- #define TEST_FP_OP2_D TEST_FP_OP2_D32
+ # Replace the functions with the 32-bit variants defined in test_macros.h
+ #undef TEST_FP_OP2_D
+ #define TEST_FP_OP2_D TEST_FP_OP2_D32
- #undef TEST_FP_OP1_D
- #define TEST_FP_OP1_D TEST_FP_OP1_D32
+ #undef TEST_FP_OP1_D
+ #define TEST_FP_OP1_D TEST_FP_OP1_D32
- #undef TEST_FP_OP1_D_DWORD_RESULT
- #define TEST_FP_OP1_D_DWORD_RESULT TEST_FP_OP1_D32_DWORD_RESULT
-#endif
+ #undef TEST_FP_OP1_D_DWORD_RESULT
+ #define TEST_FP_OP1_D_DWORD_RESULT TEST_FP_OP1_D32_DWORD_RESULT
#-------------------------------------------------------------
# Arithmetic tests
diff --git a/tests/riscv-tests/rv32ud/fmadd.S b/tests/riscv-tests/rv32ud/fmadd.S
@@ -13,11 +13,9 @@
RVTEST_RV64UF
RVTEST_CODE_BEGIN
-#if __riscv_xlen == 32
- # Replace the function with the 32-bit variant defined in test_macros.h
- #undef TEST_FP_OP3_D
- #define TEST_FP_OP3_D TEST_FP_OP3_D32
-#endif
+ # Replace the function with the 32-bit variant defined in test_macros.h
+ #undef TEST_FP_OP3_D
+ #define TEST_FP_OP3_D TEST_FP_OP3_D32
#-------------------------------------------------------------
# Arithmetic tests
diff --git a/tests/riscv-tests/rv32ud/fmin.S b/tests/riscv-tests/rv32ud/fmin.S
@@ -13,13 +13,11 @@
RVTEST_RV64UF
RVTEST_CODE_BEGIN
-#if __riscv_xlen == 32
- # Replace the function with the 32-bit variant defined in test_macros.h
- #undef TEST_FP_OP2_D
- #define TEST_FP_OP2_D TEST_FP_OP2_D32
- #undef TEST_FP_OP2_D_HEX
- #define TEST_FP_OP2_D_HEX TEST_FP_OP2_D32_HEX
-#endif
+ # Replace the function with the 32-bit variant defined in test_macros.h
+ #undef TEST_FP_OP2_D
+ #define TEST_FP_OP2_D TEST_FP_OP2_D32
+ #undef TEST_FP_OP2_D_HEX
+ #define TEST_FP_OP2_D_HEX TEST_FP_OP2_D32_HEX
#-------------------------------------------------------------
# Arithmetic tests
diff --git a/tests/riscv-tests/rv32ud/move.S b/tests/riscv-tests/rv32ud/move.S
@@ -1,113 +0,0 @@
-# See LICENSE for license details.
-
-#*****************************************************************************
-# move.S
-#-----------------------------------------------------------------------------
-#
-# This test verifies that fmv.d.x, fmv.x.d, and fsgnj[x|n].d work properly.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64UF
-RVTEST_CODE_BEGIN
-
-#TODO: make 32-bit compatible version
-#define TEST_FSGNJD(n, insn, new_sign, rs1_sign, rs2_sign) \
- TEST_CASE(n, a0, 0x123456789abcdef0 | (-(new_sign) << 63), \
- li a1, ((rs1_sign) << 63) | 0x123456789abcdef0; \
- li a2, -(rs2_sign); \
- fmv.d.x f1, a1; \
- fmv.d.x f2, a2; \
- insn f0, f1, f2; \
- fmv.x.d a0, f0)
-
- TEST_FSGNJD(10, fsgnj.d, 0, 0, 0)
- TEST_FSGNJD(11, fsgnj.d, 1, 0, 1)
- TEST_FSGNJD(12, fsgnj.d, 0, 1, 0)
- TEST_FSGNJD(13, fsgnj.d, 1, 1, 1)
-
- TEST_FSGNJD(20, fsgnjn.d, 1, 0, 0)
- TEST_FSGNJD(21, fsgnjn.d, 0, 0, 1)
- TEST_FSGNJD(22, fsgnjn.d, 1, 1, 0)
- TEST_FSGNJD(23, fsgnjn.d, 0, 1, 1)
-
- TEST_FSGNJD(30, fsgnjx.d, 0, 0, 0)
- TEST_FSGNJD(31, fsgnjx.d, 1, 0, 1)
- TEST_FSGNJD(32, fsgnjx.d, 1, 1, 0)
- TEST_FSGNJD(33, fsgnjx.d, 0, 1, 1)
-
-// Test fsgnj.s in conjunction with double-precision moves
-#define TEST_FSGNJS(n, rd, rs1, rs2) \
- TEST_CASE(n, a0, (rd) | (-((rd) >> 31) << 32), \
- li a1, rs1; \
- li a2, rs2; \
- fmv.d.x f1, a1; \
- fmv.d.x f2, a2; \
- fsgnj.s f0, f1, f2; \
- fmv.x.s a0, f0); \
- TEST_CASE(1##n, a0, (rd) | 0xffffffff00000000, \
- li a1, rs1; \
- li a2, rs2; \
- fmv.d.x f1, a1; \
- fmv.d.x f2, a2; \
- fsgnj.s f0, f1, f2; \
- fmv.x.d a0, f0)
-
- TEST_FSGNJS(40, qNaNf, 0x7ffffffe12345678, 0)
- TEST_FSGNJS(41, qNaNf, 0xfffffffe12345678, 0)
- TEST_FSGNJS(42, qNaNf, 0x7fffffff12345678, 0)
- TEST_FSGNJS(43, 0x12345678, 0xffffffff12345678, 0)
-
- TEST_FSGNJS(50, qNaNf, 0x7ffffffe12345678, 0x80000000)
- TEST_FSGNJS(51, qNaNf, 0xfffffffe12345678, 0x80000000)
- TEST_FSGNJS(52, qNaNf, 0x7fffffff12345678, 0x80000000)
- TEST_FSGNJS(53, 0x12345678, 0xffffffff12345678, 0x80000000)
-
- TEST_FSGNJS(60, 0xffc00000, 0x7ffffffe12345678, 0xffffffff80000000)
- TEST_FSGNJS(61, 0xffc00000, 0xfffffffe12345678, 0xffffffff80000000)
- TEST_FSGNJS(62, 0x92345678, 0xffffffff12345678, 0xffffffff80000000)
- TEST_FSGNJS(63, 0x12345678, 0xffffffff12345678, 0x7fffffff80000000)
-
-// Test fsgnj.d in conjunction with single-precision moves
-#define TEST_FSGNJD_SP(n, isnan, rd, rs1, rs2) \
- TEST_CASE(n, a0, ((rd) & 0xffffffff) | (-(((rd) >> 31) & 1) << 32), \
- li a1, rs1; \
- li a2, rs2; \
- fmv.d.x f1, a1; \
- fmv.d.x f2, a2; \
- fsgnj.d f0, f1, f2; \
- feq.s a0, f0, f0; \
- addi a0, a0, -!(isnan); \
- bnez a0, 1f; \
- fmv.x.s a0, f0; \
- 1:); \
- TEST_CASE(1##n, a0, rd, \
- li a1, rs1; \
- li a2, rs2; \
- fmv.d.x f1, a1; \
- fmv.d.x f2, a2; \
- fsgnj.d f0, f1, f2; \
- fmv.x.d a0, f0; \
- 1:)
-
- TEST_FSGNJD_SP(70, 0, 0xffffffff11111111, 0xffffffff11111111, 0xffffffff11111111)
- TEST_FSGNJD_SP(71, 1, 0x7fffffff11111111, 0xffffffff11111111, 0x7fffffff11111111)
- TEST_FSGNJD_SP(72, 0, 0xffffffff11111111, 0xffffffff11111111, 0xffffffff91111111)
- TEST_FSGNJD_SP(73, 0, 0xffffffff11111111, 0xffffffff11111111, 0x8000000000000000)
- TEST_FSGNJD_SP(74, 0, 0xffffffff11111111, 0x7fffffff11111111, 0xffffffff11111111)
- TEST_FSGNJD_SP(75, 1, 0x7fffffff11111111, 0x7fffffff11111111, 0x7fffffff11111111)
- TEST_FSGNJD_SP(76, 0, 0xffffffff11111111, 0x7fffffff11111111, 0xffffffff91111111)
- TEST_FSGNJD_SP(77, 0, 0xffffffff11111111, 0x7fffffff11111111, 0x8000000000000000)
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ud/structural.S b/tests/riscv-tests/rv32ud/structural.S
@@ -1,60 +0,0 @@
-# See LICENSE for license details.
-
-#*****************************************************************************
-# structural.S
-#-----------------------------------------------------------------------------
-#
-# This test verifies that the FPU correctly obviates structural hazards on its
-# writeback port (e.g. fadd followed by fsgnj)
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64UF
-RVTEST_CODE_BEGIN
-
-li x12, 1
-
-li x2, 0x3FF0000000000000
-li x1, 0x3F800000
-
-#define TEST(testnum, nops) \
-test_ ## testnum: \
- li TESTNUM, testnum; \
- fmv.d.x f4, x0 ;\
- fmv.s.x f3, x0 ;\
- fmv.d.x f2, x2 ;\
- fmv.s.x f1, x1 ;\
- j 1f ;\
- .align 5 ;\
-1:fmul.d f4, f2, f2 ;\
- nops ;\
- fsgnj.s f3, f1, f1 ;\
- fmv.x.d x4, f4 ;\
- fmv.x.s x5, f3 ;\
- beq x1, x5, 2f ;\
- j fail;\
-2:beq x2, x4, 2f ;\
- j fail; \
-2:fmv.d.x f2, zero ;\
- fmv.s.x f1, zero ;\
-
-TEST(1,;)
-TEST(2,nop)
-TEST(3,nop;nop)
-TEST(4,nop;nop;nop)
-TEST(5,nop;nop;nop;nop)
-TEST(6,nop;nop;nop;nop;nop)
-TEST(7,nop;nop;nop;nop;nop;nop)
-
-TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/addiw.S b/tests/riscv-tests/rv32ui/addiw.S
@@ -1,71 +0,0 @@
-# See LICENSE for license details.
-
-#*****************************************************************************
-# addiw.S
-#-----------------------------------------------------------------------------
-#
-# Test addiw instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- #-------------------------------------------------------------
- # Arithmetic tests
- #-------------------------------------------------------------
-
- TEST_IMM_OP( 2, addiw, 0x00000000, 0x00000000, 0x000 );
- TEST_IMM_OP( 3, addiw, 0x00000002, 0x00000001, 0x001 );
- TEST_IMM_OP( 4, addiw, 0x0000000a, 0x00000003, 0x007 );
-
- TEST_IMM_OP( 5, addiw, 0xfffffffffffff800, 0x0000000000000000, 0x800 );
- TEST_IMM_OP( 6, addiw, 0xffffffff80000000, 0xffffffff80000000, 0x000 );
- TEST_IMM_OP( 7, addiw, 0x000000007ffff800, 0xffffffff80000000, 0x800 );
-
- TEST_IMM_OP( 8, addiw, 0x00000000000007ff, 0x00000000, 0x7ff );
- TEST_IMM_OP( 9, addiw, 0x000000007fffffff, 0x7fffffff, 0x000 );
- TEST_IMM_OP( 10, addiw, 0xffffffff800007fe, 0x7fffffff, 0x7ff );
-
- TEST_IMM_OP( 11, addiw, 0xffffffff800007ff, 0xffffffff80000000, 0x7ff );
- TEST_IMM_OP( 12, addiw, 0x000000007ffff7ff, 0x000000007fffffff, 0x800 );
-
- TEST_IMM_OP( 13, addiw, 0xffffffffffffffff, 0x0000000000000000, 0xfff );
- TEST_IMM_OP( 14, addiw, 0x0000000000000000, 0xffffffffffffffff, 0x001 );
- TEST_IMM_OP( 15, addiw, 0xfffffffffffffffe, 0xffffffffffffffff, 0xfff );
-
- TEST_IMM_OP( 16, addiw, 0xffffffff80000000, 0x7fffffff, 0x001 );
-
- #-------------------------------------------------------------
- # Source/Destination tests
- #-------------------------------------------------------------
-
- TEST_IMM_SRC1_EQ_DEST( 17, addiw, 24, 13, 11 );
-
- #-------------------------------------------------------------
- # Bypassing tests
- #-------------------------------------------------------------
-
- TEST_IMM_DEST_BYPASS( 18, 0, addiw, 24, 13, 11 );
- TEST_IMM_DEST_BYPASS( 19, 1, addiw, 23, 13, 10 );
- TEST_IMM_DEST_BYPASS( 20, 2, addiw, 22, 13, 9 );
-
- TEST_IMM_SRC1_BYPASS( 21, 0, addiw, 24, 13, 11 );
- TEST_IMM_SRC1_BYPASS( 22, 1, addiw, 23, 13, 10 );
- TEST_IMM_SRC1_BYPASS( 23, 2, addiw, 22, 13, 9 );
-
- TEST_IMM_ZEROSRC1( 24, addiw, 32, 32 );
- TEST_IMM_ZERODEST( 25, addiw, 33, 50 );
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/addw.S b/tests/riscv-tests/rv32ui/addw.S
@@ -1,85 +0,0 @@
-# See LICENSE for license details.
-
-#*****************************************************************************
-# addw.S
-#-----------------------------------------------------------------------------
-#
-# Test addw instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- #-------------------------------------------------------------
- # Arithmetic tests
- #-------------------------------------------------------------
-
- TEST_RR_OP( 2, addw, 0x00000000, 0x00000000, 0x00000000 );
- TEST_RR_OP( 3, addw, 0x00000002, 0x00000001, 0x00000001 );
- TEST_RR_OP( 4, addw, 0x0000000a, 0x00000003, 0x00000007 );
-
- TEST_RR_OP( 5, addw, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 );
- TEST_RR_OP( 6, addw, 0xffffffff80000000, 0xffffffff80000000, 0x00000000 );
- TEST_RR_OP( 7, addw, 0x000000007fff8000, 0xffffffff80000000, 0xffffffffffff8000 );
-
- TEST_RR_OP( 8, addw, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff );
- TEST_RR_OP( 9, addw, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 );
- TEST_RR_OP( 10, addw, 0xffffffff80007ffe, 0x000000007fffffff, 0x0000000000007fff );
-
- TEST_RR_OP( 11, addw, 0xffffffff80007fff, 0xffffffff80000000, 0x0000000000007fff );
- TEST_RR_OP( 12, addw, 0x000000007fff7fff, 0x000000007fffffff, 0xffffffffffff8000 );
-
- TEST_RR_OP( 13, addw, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff );
- TEST_RR_OP( 14, addw, 0x0000000000000000, 0xffffffffffffffff, 0x0000000000000001 );
- TEST_RR_OP( 15, addw, 0xfffffffffffffffe, 0xffffffffffffffff, 0xffffffffffffffff );
-
- TEST_RR_OP( 16, addw, 0xffffffff80000000, 0x0000000000000001, 0x000000007fffffff );
-
- #-------------------------------------------------------------
- # Source/Destination tests
- #-------------------------------------------------------------
-
- TEST_RR_SRC1_EQ_DEST( 17, addw, 24, 13, 11 );
- TEST_RR_SRC2_EQ_DEST( 18, addw, 25, 14, 11 );
- TEST_RR_SRC12_EQ_DEST( 19, addw, 26, 13 );
-
- #-------------------------------------------------------------
- # Bypassing tests
- #-------------------------------------------------------------
-
- TEST_RR_DEST_BYPASS( 20, 0, addw, 24, 13, 11 );
- TEST_RR_DEST_BYPASS( 21, 1, addw, 25, 14, 11 );
- TEST_RR_DEST_BYPASS( 22, 2, addw, 26, 15, 11 );
-
- TEST_RR_SRC12_BYPASS( 23, 0, 0, addw, 24, 13, 11 );
- TEST_RR_SRC12_BYPASS( 24, 0, 1, addw, 25, 14, 11 );
- TEST_RR_SRC12_BYPASS( 25, 0, 2, addw, 26, 15, 11 );
- TEST_RR_SRC12_BYPASS( 26, 1, 0, addw, 24, 13, 11 );
- TEST_RR_SRC12_BYPASS( 27, 1, 1, addw, 25, 14, 11 );
- TEST_RR_SRC12_BYPASS( 28, 2, 0, addw, 26, 15, 11 );
-
- TEST_RR_SRC21_BYPASS( 29, 0, 0, addw, 24, 13, 11 );
- TEST_RR_SRC21_BYPASS( 30, 0, 1, addw, 25, 14, 11 );
- TEST_RR_SRC21_BYPASS( 31, 0, 2, addw, 26, 15, 11 );
- TEST_RR_SRC21_BYPASS( 32, 1, 0, addw, 24, 13, 11 );
- TEST_RR_SRC21_BYPASS( 33, 1, 1, addw, 25, 14, 11 );
- TEST_RR_SRC21_BYPASS( 34, 2, 0, addw, 26, 15, 11 );
-
- TEST_RR_ZEROSRC1( 35, addw, 15, 15 );
- TEST_RR_ZEROSRC2( 36, addw, 32, 32 );
- TEST_RR_ZEROSRC12( 37, addw, 0 );
- TEST_RR_ZERODEST( 38, addw, 16, 30 );
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/ld.S b/tests/riscv-tests/rv32ui/ld.S
@@ -1,92 +0,0 @@
-# See LICENSE for license details.
-
-#*****************************************************************************
-# ld.S
-#-----------------------------------------------------------------------------
-#
-# Test ld instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- #-------------------------------------------------------------
- # Basic tests
- #-------------------------------------------------------------
-
- TEST_LD_OP( 2, ld, 0x00ff00ff00ff00ff, 0, tdat );
- TEST_LD_OP( 3, ld, 0xff00ff00ff00ff00, 8, tdat );
- TEST_LD_OP( 4, ld, 0x0ff00ff00ff00ff0, 16, tdat );
- TEST_LD_OP( 5, ld, 0xf00ff00ff00ff00f, 24, tdat );
-
- # Test with negative offset
-
- TEST_LD_OP( 6, ld, 0x00ff00ff00ff00ff, -24, tdat4 );
- TEST_LD_OP( 7, ld, 0xff00ff00ff00ff00, -16, tdat4 );
- TEST_LD_OP( 8, ld, 0x0ff00ff00ff00ff0, -8, tdat4 );
- TEST_LD_OP( 9, ld, 0xf00ff00ff00ff00f, 0, tdat4 );
-
- # Test with a negative base
-
- TEST_CASE( 10, x5, 0x00ff00ff00ff00ff, \
- la x1, tdat; \
- addi x1, x1, -32; \
- ld x5, 32(x1); \
- )
-
- # Test with unaligned base
-
- TEST_CASE( 11, x5, 0xff00ff00ff00ff00, \
- la x1, tdat; \
- addi x1, x1, -3; \
- ld x5, 11(x1); \
- )
-
- #-------------------------------------------------------------
- # Bypassing tests
- #-------------------------------------------------------------
-
- TEST_LD_DEST_BYPASS( 12, 0, ld, 0x0ff00ff00ff00ff0, 8, tdat2 );
- TEST_LD_DEST_BYPASS( 13, 1, ld, 0xf00ff00ff00ff00f, 8, tdat3 );
- TEST_LD_DEST_BYPASS( 14, 2, ld, 0xff00ff00ff00ff00, 8, tdat1 );
-
- TEST_LD_SRC1_BYPASS( 15, 0, ld, 0x0ff00ff00ff00ff0, 8, tdat2 );
- TEST_LD_SRC1_BYPASS( 16, 1, ld, 0xf00ff00ff00ff00f, 8, tdat3 );
- TEST_LD_SRC1_BYPASS( 17, 2, ld, 0xff00ff00ff00ff00, 8, tdat1 );
-
- #-------------------------------------------------------------
- # Test write-after-write hazard
- #-------------------------------------------------------------
-
- TEST_CASE( 18, x2, 2, \
- la x5, tdat; \
- ld x2, 0(x5); \
- li x2, 2; \
- )
-
- TEST_CASE( 19, x2, 2, \
- la x5, tdat; \
- ld x2, 0(x5); \
- nop; \
- li x2, 2; \
- )
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-tdat:
-tdat1: .dword 0x00ff00ff00ff00ff
-tdat2: .dword 0xff00ff00ff00ff00
-tdat3: .dword 0x0ff00ff00ff00ff0
-tdat4: .dword 0xf00ff00ff00ff00f
-
-RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/lwu.S b/tests/riscv-tests/rv32ui/lwu.S
@@ -1,92 +0,0 @@
-# See LICENSE for license details.
-
-#*****************************************************************************
-# lwu.S
-#-----------------------------------------------------------------------------
-#
-# Test lwu instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- #-------------------------------------------------------------
- # Basic tests
- #-------------------------------------------------------------
-
- TEST_LD_OP( 2, lwu, 0x0000000000ff00ff, 0, tdat );
- TEST_LD_OP( 3, lwu, 0x00000000ff00ff00, 4, tdat );
- TEST_LD_OP( 4, lwu, 0x000000000ff00ff0, 8, tdat );
- TEST_LD_OP( 5, lwu, 0x00000000f00ff00f, 12, tdat );
-
- # Test with negative offset
-
- TEST_LD_OP( 6, lwu, 0x0000000000ff00ff, -12, tdat4 );
- TEST_LD_OP( 7, lwu, 0x00000000ff00ff00, -8, tdat4 );
- TEST_LD_OP( 8, lwu, 0x000000000ff00ff0, -4, tdat4 );
- TEST_LD_OP( 9, lwu, 0x00000000f00ff00f, 0, tdat4 );
-
- # Test with a negative base
-
- TEST_CASE( 10, x5, 0x0000000000ff00ff, \
- la x1, tdat; \
- addi x1, x1, -32; \
- lwu x5, 32(x1); \
- )
-
- # Test with unaligned base
-
- TEST_CASE( 11, x5, 0x00000000ff00ff00, \
- la x1, tdat; \
- addi x1, x1, -3; \
- lwu x5, 7(x1); \
- )
-
- #-------------------------------------------------------------
- # Bypassing tests
- #-------------------------------------------------------------
-
- TEST_LD_DEST_BYPASS( 12, 0, lwu, 0x000000000ff00ff0, 4, tdat2 );
- TEST_LD_DEST_BYPASS( 13, 1, lwu, 0x00000000f00ff00f, 4, tdat3 );
- TEST_LD_DEST_BYPASS( 14, 2, lwu, 0x00000000ff00ff00, 4, tdat1 );
-
- TEST_LD_SRC1_BYPASS( 15, 0, lwu, 0x000000000ff00ff0, 4, tdat2 );
- TEST_LD_SRC1_BYPASS( 16, 1, lwu, 0x00000000f00ff00f, 4, tdat3 );
- TEST_LD_SRC1_BYPASS( 17, 2, lwu, 0x00000000ff00ff00, 4, tdat1 );
-
- #-------------------------------------------------------------
- # Test write-after-write hazard
- #-------------------------------------------------------------
-
- TEST_CASE( 18, x2, 2, \
- la x5, tdat; \
- lwu x2, 0(x5); \
- li x2, 2; \
- )
-
- TEST_CASE( 19, x2, 2, \
- la x5, tdat; \
- lwu x2, 0(x5); \
- nop; \
- li x2, 2; \
- )
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-tdat:
-tdat1: .word 0x00ff00ff
-tdat2: .word 0xff00ff00
-tdat3: .word 0x0ff00ff0
-tdat4: .word 0xf00ff00f
-
-RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/sd.S b/tests/riscv-tests/rv32ui/sd.S
@@ -1,92 +0,0 @@
-# See LICENSE for license details.
-
-#*****************************************************************************
-# sd.S
-#-----------------------------------------------------------------------------
-#
-# Test sd instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- #-------------------------------------------------------------
- # Basic tests
- #-------------------------------------------------------------
-
- TEST_ST_OP( 2, ld, sd, 0x00aa00aa00aa00aa, 0, tdat );
- TEST_ST_OP( 3, ld, sd, 0xaa00aa00aa00aa00, 8, tdat );
- TEST_ST_OP( 4, ld, sd, 0x0aa00aa00aa00aa0, 16, tdat );
- TEST_ST_OP( 5, ld, sd, 0xa00aa00aa00aa00a, 24, tdat );
-
- # Test with negative offset
-
- TEST_ST_OP( 6, ld, sd, 0x00aa00aa00aa00aa, -24, tdat8 );
- TEST_ST_OP( 7, ld, sd, 0xaa00aa00aa00aa00, -16, tdat8 );
- TEST_ST_OP( 8, ld, sd, 0x0aa00aa00aa00aa0, -8, tdat8 );
- TEST_ST_OP( 9, ld, sd, 0xa00aa00aa00aa00a, 0, tdat8 );
-
- # Test with a negative base
-
- TEST_CASE( 10, x5, 0x1234567812345678, \
- la x1, tdat9; \
- li x2, 0x1234567812345678; \
- addi x4, x1, -32; \
- sd x2, 32(x4); \
- ld x5, 0(x1); \
- )
-
- # Test with unaligned base
-
- TEST_CASE( 11, x5, 0x5821309858213098, \
- la x1, tdat9; \
- li x2, 0x5821309858213098; \
- addi x1, x1, -3; \
- sd x2, 11(x1); \
- la x4, tdat10; \
- ld x5, 0(x4); \
- )
-
- #-------------------------------------------------------------
- # Bypassing tests
- #-------------------------------------------------------------
-
- TEST_ST_SRC12_BYPASS( 12, 0, 0, ld, sd, 0xabbccdd, 0, tdat );
- TEST_ST_SRC12_BYPASS( 13, 0, 1, ld, sd, 0xaabbccd, 8, tdat );
- TEST_ST_SRC12_BYPASS( 14, 0, 2, ld, sd, 0xdaabbcc, 16, tdat );
- TEST_ST_SRC12_BYPASS( 15, 1, 0, ld, sd, 0xddaabbc, 24, tdat );
- TEST_ST_SRC12_BYPASS( 16, 1, 1, ld, sd, 0xcddaabb, 32, tdat );
- TEST_ST_SRC12_BYPASS( 17, 2, 0, ld, sd, 0xccddaab, 40, tdat );
-
- TEST_ST_SRC21_BYPASS( 18, 0, 0, ld, sd, 0x00112233, 0, tdat );
- TEST_ST_SRC21_BYPASS( 19, 0, 1, ld, sd, 0x30011223, 8, tdat );
- TEST_ST_SRC21_BYPASS( 20, 0, 2, ld, sd, 0x33001122, 16, tdat );
- TEST_ST_SRC21_BYPASS( 21, 1, 0, ld, sd, 0x23300112, 24, tdat );
- TEST_ST_SRC21_BYPASS( 22, 1, 1, ld, sd, 0x22330011, 32, tdat );
- TEST_ST_SRC21_BYPASS( 23, 2, 0, ld, sd, 0x12233001, 40, tdat );
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-tdat:
-tdat1: .dword 0xdeadbeefdeadbeef
-tdat2: .dword 0xdeadbeefdeadbeef
-tdat3: .dword 0xdeadbeefdeadbeef
-tdat4: .dword 0xdeadbeefdeadbeef
-tdat5: .dword 0xdeadbeefdeadbeef
-tdat6: .dword 0xdeadbeefdeadbeef
-tdat7: .dword 0xdeadbeefdeadbeef
-tdat8: .dword 0xdeadbeefdeadbeef
-tdat9: .dword 0xdeadbeefdeadbeef
-tdat10: .dword 0xdeadbeefdeadbeef
-
-RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/slliw.S b/tests/riscv-tests/rv32ui/slliw.S
@@ -1,75 +0,0 @@
-# See LICENSE for license details.
-
-#*****************************************************************************
-# slliw.S
-#-----------------------------------------------------------------------------
-#
-# Test slliw instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- #-------------------------------------------------------------
- # Arithmetic tests
- #-------------------------------------------------------------
-
- TEST_IMM_OP( 2, slliw, 0x0000000000000001, 0x0000000000000001, 0 );
- TEST_IMM_OP( 3, slliw, 0x0000000000000002, 0x0000000000000001, 1 );
- TEST_IMM_OP( 4, slliw, 0x0000000000000080, 0x0000000000000001, 7 );
- TEST_IMM_OP( 5, slliw, 0x0000000000004000, 0x0000000000000001, 14 );
- TEST_IMM_OP( 6, slliw, 0xffffffff80000000, 0x0000000000000001, 31 );
-
- TEST_IMM_OP( 7, slliw, 0xffffffffffffffff, 0xffffffffffffffff, 0 );
- TEST_IMM_OP( 8, slliw, 0xfffffffffffffffe, 0xffffffffffffffff, 1 );
- TEST_IMM_OP( 9, slliw, 0xffffffffffffff80, 0xffffffffffffffff, 7 );
- TEST_IMM_OP( 10, slliw, 0xffffffffffffc000, 0xffffffffffffffff, 14 );
- TEST_IMM_OP( 11, slliw, 0xffffffff80000000, 0xffffffffffffffff, 31 );
-
- TEST_IMM_OP( 12, slliw, 0x0000000021212121, 0x0000000021212121, 0 );
- TEST_IMM_OP( 13, slliw, 0x0000000042424242, 0x0000000021212121, 1 );
- TEST_IMM_OP( 14, slliw, 0xffffffff90909080, 0x0000000021212121, 7 );
- TEST_IMM_OP( 15, slliw, 0x0000000048484000, 0x0000000021212121, 14 );
- TEST_IMM_OP( 16, slliw, 0xffffffff80000000, 0x0000000021212121, 31 );
-
- # Verify that shifts ignore top 32 (using true 64-bit values)
-
- TEST_IMM_OP( 44, slliw, 0x0000000012345678, 0xffffffff12345678, 0 );
- TEST_IMM_OP( 45, slliw, 0x0000000023456780, 0xffffffff12345678, 4 );
- TEST_IMM_OP( 46, slliw, 0xffffffff92345678, 0x0000000092345678, 0 );
- TEST_IMM_OP( 47, slliw, 0xffffffff93456780, 0x0000000099345678, 4 );
-
- #-------------------------------------------------------------
- # Source/Destination tests
- #-------------------------------------------------------------
-
- TEST_IMM_SRC1_EQ_DEST( 17, slliw, 0x00000080, 0x00000001, 7 );
-
- #-------------------------------------------------------------
- # Bypassing tests
- #-------------------------------------------------------------
-
- TEST_IMM_DEST_BYPASS( 18, 0, slliw, 0x0000000000000080, 0x0000000000000001, 7 );
- TEST_IMM_DEST_BYPASS( 19, 1, slliw, 0x0000000000004000, 0x0000000000000001, 14 );
- TEST_IMM_DEST_BYPASS( 20, 2, slliw, 0xffffffff80000000, 0x0000000000000001, 31 );
-
- TEST_IMM_SRC1_BYPASS( 21, 0, slliw, 0x0000000000000080, 0x0000000000000001, 7 );
- TEST_IMM_SRC1_BYPASS( 22, 1, slliw, 0x0000000000004000, 0x0000000000000001, 14 );
- TEST_IMM_SRC1_BYPASS( 23, 2, slliw, 0xffffffff80000000, 0x0000000000000001, 31 );
-
- TEST_IMM_ZEROSRC1( 24, slliw, 0, 31 );
- TEST_IMM_ZERODEST( 25, slliw, 31, 28 );
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/sllw.S b/tests/riscv-tests/rv32ui/sllw.S
@@ -1,97 +0,0 @@
-# See LICENSE for license details.
-
-#*****************************************************************************
-# sllw.S
-#-----------------------------------------------------------------------------
-#
-# Test sllw instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- #-------------------------------------------------------------
- # Arithmetic tests
- #-------------------------------------------------------------
-
- TEST_RR_OP( 2, sllw, 0x0000000000000001, 0x0000000000000001, 0 );
- TEST_RR_OP( 3, sllw, 0x0000000000000002, 0x0000000000000001, 1 );
- TEST_RR_OP( 4, sllw, 0x0000000000000080, 0x0000000000000001, 7 );
- TEST_RR_OP( 5, sllw, 0x0000000000004000, 0x0000000000000001, 14 );
- TEST_RR_OP( 6, sllw, 0xffffffff80000000, 0x0000000000000001, 31 );
-
- TEST_RR_OP( 7, sllw, 0xffffffffffffffff, 0xffffffffffffffff, 0 );
- TEST_RR_OP( 8, sllw, 0xfffffffffffffffe, 0xffffffffffffffff, 1 );
- TEST_RR_OP( 9, sllw, 0xffffffffffffff80, 0xffffffffffffffff, 7 );
- TEST_RR_OP( 10, sllw, 0xffffffffffffc000, 0xffffffffffffffff, 14 );
- TEST_RR_OP( 11, sllw, 0xffffffff80000000, 0xffffffffffffffff, 31 );
-
- TEST_RR_OP( 12, sllw, 0x0000000021212121, 0x0000000021212121, 0 );
- TEST_RR_OP( 13, sllw, 0x0000000042424242, 0x0000000021212121, 1 );
- TEST_RR_OP( 14, sllw, 0xffffffff90909080, 0x0000000021212121, 7 );
- TEST_RR_OP( 15, sllw, 0x0000000048484000, 0x0000000021212121, 14 );
- TEST_RR_OP( 16, sllw, 0xffffffff80000000, 0x0000000021212121, 31 );
-
- # Verify that shifts only use bottom five bits
-
- TEST_RR_OP( 17, sllw, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffe0 );
- TEST_RR_OP( 18, sllw, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffe1 );
- TEST_RR_OP( 19, sllw, 0xffffffff90909080, 0x0000000021212121, 0xffffffffffffffe7 );
- TEST_RR_OP( 20, sllw, 0x0000000048484000, 0x0000000021212121, 0xffffffffffffffee );
- TEST_RR_OP( 21, sllw, 0xffffffff80000000, 0x0000000021212121, 0xffffffffffffffff );
-
- # Verify that shifts ignore top 32 (using true 64-bit values)
-
- TEST_RR_OP( 44, sllw, 0x0000000012345678, 0xffffffff12345678, 0 );
- TEST_RR_OP( 45, sllw, 0x0000000023456780, 0xffffffff12345678, 4 );
- TEST_RR_OP( 46, sllw, 0xffffffff92345678, 0x0000000092345678, 0 );
- TEST_RR_OP( 47, sllw, 0xffffffff93456780, 0x0000000099345678, 4 );
-
- #-------------------------------------------------------------
- # Source/Destination tests
- #-------------------------------------------------------------
-
- TEST_RR_SRC1_EQ_DEST( 22, sllw, 0x00000080, 0x00000001, 7 );
- TEST_RR_SRC2_EQ_DEST( 23, sllw, 0x00004000, 0x00000001, 14 );
- TEST_RR_SRC12_EQ_DEST( 24, sllw, 24, 3 );
-
- #-------------------------------------------------------------
- # Bypassing tests
- #-------------------------------------------------------------
-
- TEST_RR_DEST_BYPASS( 25, 0, sllw, 0x0000000000000080, 0x0000000000000001, 7 );
- TEST_RR_DEST_BYPASS( 26, 1, sllw, 0x0000000000004000, 0x0000000000000001, 14 );
- TEST_RR_DEST_BYPASS( 27, 2, sllw, 0xffffffff80000000, 0x0000000000000001, 31 );
-
- TEST_RR_SRC12_BYPASS( 28, 0, 0, sllw, 0x0000000000000080, 0x0000000000000001, 7 );
- TEST_RR_SRC12_BYPASS( 29, 0, 1, sllw, 0x0000000000004000, 0x0000000000000001, 14 );
- TEST_RR_SRC12_BYPASS( 30, 0, 2, sllw, 0xffffffff80000000, 0x0000000000000001, 31 );
- TEST_RR_SRC12_BYPASS( 31, 1, 0, sllw, 0x0000000000000080, 0x0000000000000001, 7 );
- TEST_RR_SRC12_BYPASS( 32, 1, 1, sllw, 0x0000000000004000, 0x0000000000000001, 14 );
- TEST_RR_SRC12_BYPASS( 33, 2, 0, sllw, 0xffffffff80000000, 0x0000000000000001, 31 );
-
- TEST_RR_SRC21_BYPASS( 34, 0, 0, sllw, 0x0000000000000080, 0x0000000000000001, 7 );
- TEST_RR_SRC21_BYPASS( 35, 0, 1, sllw, 0x0000000000004000, 0x0000000000000001, 14 );
- TEST_RR_SRC21_BYPASS( 36, 0, 2, sllw, 0xffffffff80000000, 0x0000000000000001, 31 );
- TEST_RR_SRC21_BYPASS( 37, 1, 0, sllw, 0x0000000000000080, 0x0000000000000001, 7 );
- TEST_RR_SRC21_BYPASS( 38, 1, 1, sllw, 0x0000000000004000, 0x0000000000000001, 14 );
- TEST_RR_SRC21_BYPASS( 39, 2, 0, sllw, 0xffffffff80000000, 0x0000000000000001, 31 );
-
- TEST_RR_ZEROSRC1( 40, sllw, 0, 15 );
- TEST_RR_ZEROSRC2( 41, sllw, 32, 32 );
- TEST_RR_ZEROSRC12( 42, sllw, 0 );
- TEST_RR_ZERODEST( 43, sllw, 1024, 2048 );
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/sraiw.S b/tests/riscv-tests/rv32ui/sraiw.S
@@ -1,78 +0,0 @@
-# See LICENSE for license details.
-
-#*****************************************************************************
-# sraiw.S
-#-----------------------------------------------------------------------------
-#
-# Test sraiw instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- #-------------------------------------------------------------
- # Arithmetic tests
- #-------------------------------------------------------------
-
- TEST_IMM_OP( 2, sraiw, 0xffffffff80000000, 0xffffffff80000000, 0 );
- TEST_IMM_OP( 3, sraiw, 0xffffffffc0000000, 0xffffffff80000000, 1 );
- TEST_IMM_OP( 4, sraiw, 0xffffffffff000000, 0xffffffff80000000, 7 );
- TEST_IMM_OP( 5, sraiw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
- TEST_IMM_OP( 6, sraiw, 0xffffffffffffffff, 0xffffffff80000001, 31 );
-
- TEST_IMM_OP( 7, sraiw, 0x000000007fffffff, 0x000000007fffffff, 0 );
- TEST_IMM_OP( 8, sraiw, 0x000000003fffffff, 0x000000007fffffff, 1 );
- TEST_IMM_OP( 9, sraiw, 0x0000000000ffffff, 0x000000007fffffff, 7 );
- TEST_IMM_OP( 10, sraiw, 0x000000000001ffff, 0x000000007fffffff, 14 );
- TEST_IMM_OP( 11, sraiw, 0x0000000000000000, 0x000000007fffffff, 31 );
-
- TEST_IMM_OP( 12, sraiw, 0xffffffff81818181, 0xffffffff81818181, 0 );
- TEST_IMM_OP( 13, sraiw, 0xffffffffc0c0c0c0, 0xffffffff81818181, 1 );
- TEST_IMM_OP( 14, sraiw, 0xffffffffff030303, 0xffffffff81818181, 7 );
- TEST_IMM_OP( 15, sraiw, 0xfffffffffffe0606, 0xffffffff81818181, 14 );
- TEST_IMM_OP( 16, sraiw, 0xffffffffffffffff, 0xffffffff81818181, 31 );
-
- # Verify that shifts ignore top 32 (using true 64-bit values)
-
- TEST_IMM_OP( 44, sraiw, 0x0000000012345678, 0xffffffff12345678, 0 );
- TEST_IMM_OP( 45, sraiw, 0x0000000001234567, 0xffffffff12345678, 4 );
- TEST_IMM_OP( 46, sraiw, 0xffffffff92345678, 0x0000000092345678, 0 );
- TEST_IMM_OP( 47, sraiw, 0xfffffffff9234567, 0x0000000092345678, 4 );
-
- #-------------------------------------------------------------
- # Source/Destination tests
- #-------------------------------------------------------------
-
- TEST_IMM_SRC1_EQ_DEST( 17, sraiw, 0xffffffffff000000, 0xffffffff80000000, 7 );
-
- #-------------------------------------------------------------
- # Bypassing tests
- #-------------------------------------------------------------
-
- TEST_IMM_DEST_BYPASS( 18, 0, sraiw, 0xffffffffff000000, 0xffffffff80000000, 7 );
- TEST_IMM_DEST_BYPASS( 19, 1, sraiw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
- TEST_IMM_DEST_BYPASS( 20, 2, sraiw, 0xffffffffffffffff, 0xffffffff80000001, 31 );
-
- TEST_IMM_SRC1_BYPASS( 21, 0, sraiw, 0xffffffffff000000, 0xffffffff80000000, 7 );
- TEST_IMM_SRC1_BYPASS( 22, 1, sraiw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
- TEST_IMM_SRC1_BYPASS( 23, 2, sraiw, 0xffffffffffffffff, 0xffffffff80000001, 31 );
-
- TEST_IMM_ZEROSRC1( 24, sraiw, 0, 31 );
- TEST_IMM_ZERODEST( 25, sraiw, 31, 28 );
-
- TEST_IMM_OP( 26, sraiw, 0x0000000000000000, 0x00e0000000000000, 28)
- TEST_IMM_OP( 27, sraiw, 0xffffffffff000000, 0x00000000f0000000, 4)
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/sraw.S b/tests/riscv-tests/rv32ui/sraw.S
@@ -1,97 +0,0 @@
-# See LICENSE for license details.
-
-#*****************************************************************************
-# sraw.S
-#-----------------------------------------------------------------------------
-#
-# Test sraw instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- #-------------------------------------------------------------
- # Arithmetic tests
- #-------------------------------------------------------------
-
- TEST_RR_OP( 2, sraw, 0xffffffff80000000, 0xffffffff80000000, 0 );
- TEST_RR_OP( 3, sraw, 0xffffffffc0000000, 0xffffffff80000000, 1 );
- TEST_RR_OP( 4, sraw, 0xffffffffff000000, 0xffffffff80000000, 7 );
- TEST_RR_OP( 5, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
- TEST_RR_OP( 6, sraw, 0xffffffffffffffff, 0xffffffff80000001, 31 );
-
- TEST_RR_OP( 7, sraw, 0x000000007fffffff, 0x000000007fffffff, 0 );
- TEST_RR_OP( 8, sraw, 0x000000003fffffff, 0x000000007fffffff, 1 );
- TEST_RR_OP( 9, sraw, 0x0000000000ffffff, 0x000000007fffffff, 7 );
- TEST_RR_OP( 10, sraw, 0x000000000001ffff, 0x000000007fffffff, 14 );
- TEST_RR_OP( 11, sraw, 0x0000000000000000, 0x000000007fffffff, 31 );
-
- TEST_RR_OP( 12, sraw, 0xffffffff81818181, 0xffffffff81818181, 0 );
- TEST_RR_OP( 13, sraw, 0xffffffffc0c0c0c0, 0xffffffff81818181, 1 );
- TEST_RR_OP( 14, sraw, 0xffffffffff030303, 0xffffffff81818181, 7 );
- TEST_RR_OP( 15, sraw, 0xfffffffffffe0606, 0xffffffff81818181, 14 );
- TEST_RR_OP( 16, sraw, 0xffffffffffffffff, 0xffffffff81818181, 31 );
-
- # Verify that shifts only use bottom five bits
-
- TEST_RR_OP( 17, sraw, 0xffffffff81818181, 0xffffffff81818181, 0xffffffffffffffe0 );
- TEST_RR_OP( 18, sraw, 0xffffffffc0c0c0c0, 0xffffffff81818181, 0xffffffffffffffe1 );
- TEST_RR_OP( 19, sraw, 0xffffffffff030303, 0xffffffff81818181, 0xffffffffffffffe7 );
- TEST_RR_OP( 20, sraw, 0xfffffffffffe0606, 0xffffffff81818181, 0xffffffffffffffee );
- TEST_RR_OP( 21, sraw, 0xffffffffffffffff, 0xffffffff81818181, 0xffffffffffffffff );
-
- # Verify that shifts ignore top 32 (using true 64-bit values)
-
- TEST_RR_OP( 44, sraw, 0x0000000012345678, 0xffffffff12345678, 0 );
- TEST_RR_OP( 45, sraw, 0x0000000001234567, 0xffffffff12345678, 4 );
- TEST_RR_OP( 46, sraw, 0xffffffff92345678, 0x0000000092345678, 0 );
- TEST_RR_OP( 47, sraw, 0xfffffffff9234567, 0x0000000092345678, 4 );
-
- #-------------------------------------------------------------
- # Source/Destination tests
- #-------------------------------------------------------------
-
- TEST_RR_SRC1_EQ_DEST( 22, sraw, 0xffffffffff000000, 0xffffffff80000000, 7 );
- TEST_RR_SRC2_EQ_DEST( 23, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
- TEST_RR_SRC12_EQ_DEST( 24, sraw, 0, 7 );
-
- #-------------------------------------------------------------
- # Bypassing tests
- #-------------------------------------------------------------
-
- TEST_RR_DEST_BYPASS( 25, 0, sraw, 0xffffffffff000000, 0xffffffff80000000, 7 );
- TEST_RR_DEST_BYPASS( 26, 1, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
- TEST_RR_DEST_BYPASS( 27, 2, sraw, 0xffffffffffffffff, 0xffffffff80000000, 31 );
-
- TEST_RR_SRC12_BYPASS( 28, 0, 0, sraw, 0xffffffffff000000, 0xffffffff80000000, 7 );
- TEST_RR_SRC12_BYPASS( 29, 0, 1, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
- TEST_RR_SRC12_BYPASS( 30, 0, 2, sraw, 0xffffffffffffffff, 0xffffffff80000000, 31 );
- TEST_RR_SRC12_BYPASS( 31, 1, 0, sraw, 0xffffffffff000000, 0xffffffff80000000, 7 );
- TEST_RR_SRC12_BYPASS( 32, 1, 1, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
- TEST_RR_SRC12_BYPASS( 33, 2, 0, sraw, 0xffffffffffffffff, 0xffffffff80000000, 31 );
-
- TEST_RR_SRC21_BYPASS( 34, 0, 0, sraw, 0xffffffffff000000, 0xffffffff80000000, 7 );
- TEST_RR_SRC21_BYPASS( 35, 0, 1, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
- TEST_RR_SRC21_BYPASS( 36, 0, 2, sraw, 0xffffffffffffffff, 0xffffffff80000000, 31 );
- TEST_RR_SRC21_BYPASS( 37, 1, 0, sraw, 0xffffffffff000000, 0xffffffff80000000, 7 );
- TEST_RR_SRC21_BYPASS( 38, 1, 1, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
- TEST_RR_SRC21_BYPASS( 39, 2, 0, sraw, 0xffffffffffffffff, 0xffffffff80000000, 31 );
-
- TEST_RR_ZEROSRC1( 40, sraw, 0, 15 );
- TEST_RR_ZEROSRC2( 41, sraw, 32, 32 );
- TEST_RR_ZEROSRC12( 42, sraw, 0 );
- TEST_RR_ZERODEST( 43, sraw, 1024, 2048 );
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/srliw.S b/tests/riscv-tests/rv32ui/srliw.S
@@ -1,75 +0,0 @@
-# See LICENSE for license details.
-
-#*****************************************************************************
-# srliw.S
-#-----------------------------------------------------------------------------
-#
-# Test srliw instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- #-------------------------------------------------------------
- # Arithmetic tests
- #-------------------------------------------------------------
-
- TEST_IMM_OP( 2, srliw, 0xffffffff80000000, 0xffffffff80000000, 0 );
- TEST_IMM_OP( 3, srliw, 0x0000000040000000, 0xffffffff80000000, 1 );
- TEST_IMM_OP( 4, srliw, 0x0000000001000000, 0xffffffff80000000, 7 );
- TEST_IMM_OP( 5, srliw, 0x0000000000020000, 0xffffffff80000000, 14 );
- TEST_IMM_OP( 6, srliw, 0x0000000000000001, 0xffffffff80000001, 31 );
-
- TEST_IMM_OP( 7, srliw, 0xffffffffffffffff, 0xffffffffffffffff, 0 );
- TEST_IMM_OP( 8, srliw, 0x000000007fffffff, 0xffffffffffffffff, 1 );
- TEST_IMM_OP( 9, srliw, 0x0000000001ffffff, 0xffffffffffffffff, 7 );
- TEST_IMM_OP( 10, srliw, 0x000000000003ffff, 0xffffffffffffffff, 14 );
- TEST_IMM_OP( 11, srliw, 0x0000000000000001, 0xffffffffffffffff, 31 );
-
- TEST_IMM_OP( 12, srliw, 0x0000000021212121, 0x0000000021212121, 0 );
- TEST_IMM_OP( 13, srliw, 0x0000000010909090, 0x0000000021212121, 1 );
- TEST_IMM_OP( 14, srliw, 0x0000000000424242, 0x0000000021212121, 7 );
- TEST_IMM_OP( 15, srliw, 0x0000000000008484, 0x0000000021212121, 14 );
- TEST_IMM_OP( 16, srliw, 0x0000000000000000, 0x0000000021212121, 31 );
-
- # Verify that shifts ignore top 32 (using true 64-bit values)
-
- TEST_IMM_OP( 44, srliw, 0x0000000012345678, 0xffffffff12345678, 0 );
- TEST_IMM_OP( 45, srliw, 0x0000000001234567, 0xffffffff12345678, 4 );
- TEST_IMM_OP( 46, srliw, 0xffffffff92345678, 0x0000000092345678, 0 );
- TEST_IMM_OP( 47, srliw, 0x0000000009234567, 0x0000000092345678, 4 );
-
- #-------------------------------------------------------------
- # Source/Destination tests
- #-------------------------------------------------------------
-
- TEST_IMM_SRC1_EQ_DEST( 17, srliw, 0x0000000001000000, 0xffffffff80000000, 7 );
-
- #-------------------------------------------------------------
- # Bypassing tests
- #-------------------------------------------------------------
-
- TEST_IMM_DEST_BYPASS( 18, 0, srliw, 0x0000000001000000, 0xffffffff80000000, 7 );
- TEST_IMM_DEST_BYPASS( 19, 1, srliw, 0x0000000000020000, 0xffffffff80000000, 14 );
- TEST_IMM_DEST_BYPASS( 20, 2, srliw, 0x0000000000000001, 0xffffffff80000001, 31 );
-
- TEST_IMM_SRC1_BYPASS( 21, 0, srliw, 0x0000000001000000, 0xffffffff80000000, 7 );
- TEST_IMM_SRC1_BYPASS( 22, 1, srliw, 0x0000000000020000, 0xffffffff80000000, 14 );
- TEST_IMM_SRC1_BYPASS( 23, 2, srliw, 0x0000000000000001, 0xffffffff80000001, 31 );
-
- TEST_IMM_ZEROSRC1( 24, srliw, 0, 31 );
- TEST_IMM_ZERODEST( 25, srliw, 31, 28 );
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/srlw.S b/tests/riscv-tests/rv32ui/srlw.S
@@ -1,97 +0,0 @@
-# See LICENSE for license details.
-
-#*****************************************************************************
-# srlw.S
-#-----------------------------------------------------------------------------
-#
-# Test srlw instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- #-------------------------------------------------------------
- # Arithmetic tests
- #-------------------------------------------------------------
-
- TEST_RR_OP( 2, srlw, 0xffffffff80000000, 0xffffffff80000000, 0 );
- TEST_RR_OP( 3, srlw, 0x0000000040000000, 0xffffffff80000000, 1 );
- TEST_RR_OP( 4, srlw, 0x0000000001000000, 0xffffffff80000000, 7 );
- TEST_RR_OP( 5, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
- TEST_RR_OP( 6, srlw, 0x0000000000000001, 0xffffffff80000001, 31 );
-
- TEST_RR_OP( 7, srlw, 0xffffffffffffffff, 0xffffffffffffffff, 0 );
- TEST_RR_OP( 8, srlw, 0x000000007fffffff, 0xffffffffffffffff, 1 );
- TEST_RR_OP( 9, srlw, 0x0000000001ffffff, 0xffffffffffffffff, 7 );
- TEST_RR_OP( 10, srlw, 0x000000000003ffff, 0xffffffffffffffff, 14 );
- TEST_RR_OP( 11, srlw, 0x0000000000000001, 0xffffffffffffffff, 31 );
-
- TEST_RR_OP( 12, srlw, 0x0000000021212121, 0x0000000021212121, 0 );
- TEST_RR_OP( 13, srlw, 0x0000000010909090, 0x0000000021212121, 1 );
- TEST_RR_OP( 14, srlw, 0x0000000000424242, 0x0000000021212121, 7 );
- TEST_RR_OP( 15, srlw, 0x0000000000008484, 0x0000000021212121, 14 );
- TEST_RR_OP( 16, srlw, 0x0000000000000000, 0x0000000021212121, 31 );
-
- # Verify that shifts only use bottom five bits
-
- TEST_RR_OP( 17, srlw, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffe0 );
- TEST_RR_OP( 18, srlw, 0x0000000010909090, 0x0000000021212121, 0xffffffffffffffe1 );
- TEST_RR_OP( 19, srlw, 0x0000000000424242, 0x0000000021212121, 0xffffffffffffffe7 );
- TEST_RR_OP( 20, srlw, 0x0000000000008484, 0x0000000021212121, 0xffffffffffffffee );
- TEST_RR_OP( 21, srlw, 0x0000000000000000, 0x0000000021212121, 0xffffffffffffffff );
-
- # Verify that shifts ignore top 32 (using true 64-bit values)
-
- TEST_RR_OP( 44, srlw, 0x0000000012345678, 0xffffffff12345678, 0 );
- TEST_RR_OP( 45, srlw, 0x0000000001234567, 0xffffffff12345678, 4 );
- TEST_RR_OP( 46, srlw, 0xffffffff92345678, 0x0000000092345678, 0 );
- TEST_RR_OP( 47, srlw, 0x0000000009234567, 0x0000000092345678, 4 );
-
- #-------------------------------------------------------------
- # Source/Destination tests
- #-------------------------------------------------------------
-
- TEST_RR_SRC1_EQ_DEST( 22, srlw, 0x0000000001000000, 0xffffffff80000000, 7 );
- TEST_RR_SRC2_EQ_DEST( 23, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
- TEST_RR_SRC12_EQ_DEST( 24, srlw, 0, 7 );
-
- #-------------------------------------------------------------
- # Bypassing tests
- #-------------------------------------------------------------
-
- TEST_RR_DEST_BYPASS( 25, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7 );
- TEST_RR_DEST_BYPASS( 26, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
- TEST_RR_DEST_BYPASS( 27, 2, srlw, 0x0000000000000001, 0xffffffff80000000, 31 );
-
- TEST_RR_SRC12_BYPASS( 28, 0, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7 );
- TEST_RR_SRC12_BYPASS( 29, 0, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
- TEST_RR_SRC12_BYPASS( 30, 0, 2, srlw, 0x0000000000000001, 0xffffffff80000000, 31 );
- TEST_RR_SRC12_BYPASS( 31, 1, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7 );
- TEST_RR_SRC12_BYPASS( 32, 1, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
- TEST_RR_SRC12_BYPASS( 33, 2, 0, srlw, 0x0000000000000001, 0xffffffff80000000, 31 );
-
- TEST_RR_SRC21_BYPASS( 34, 0, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7 );
- TEST_RR_SRC21_BYPASS( 35, 0, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
- TEST_RR_SRC21_BYPASS( 36, 0, 2, srlw, 0x0000000000000001, 0xffffffff80000000, 31 );
- TEST_RR_SRC21_BYPASS( 37, 1, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7 );
- TEST_RR_SRC21_BYPASS( 38, 1, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
- TEST_RR_SRC21_BYPASS( 39, 2, 0, srlw, 0x0000000000000001, 0xffffffff80000000, 31 );
-
- TEST_RR_ZEROSRC1( 40, srlw, 0, 15 );
- TEST_RR_ZEROSRC2( 41, srlw, 32, 32 );
- TEST_RR_ZEROSRC12( 42, srlw, 0 );
- TEST_RR_ZERODEST( 43, srlw, 1024, 2048 );
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/subw.S b/tests/riscv-tests/rv32ui/subw.S
@@ -1,83 +0,0 @@
-# See LICENSE for license details.
-
-#*****************************************************************************
-# subw.S
-#-----------------------------------------------------------------------------
-#
-# Test subw instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- #-------------------------------------------------------------
- # Arithmetic tests
- #-------------------------------------------------------------
-
- TEST_RR_OP( 2, subw, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000 );
- TEST_RR_OP( 3, subw, 0x0000000000000000, 0x0000000000000001, 0x0000000000000001 );
- TEST_RR_OP( 4, subw, 0xfffffffffffffffc, 0x0000000000000003, 0x0000000000000007 );
-
- TEST_RR_OP( 5, subw, 0x0000000000008000, 0x0000000000000000, 0xffffffffffff8000 );
- TEST_RR_OP( 6, subw, 0xffffffff80000000, 0xffffffff80000000, 0x0000000000000000 );
- TEST_RR_OP( 7, subw, 0xffffffff80008000, 0xffffffff80000000, 0xffffffffffff8000 );
-
- TEST_RR_OP( 8, subw, 0xffffffffffff8001, 0x0000000000000000, 0x0000000000007fff );
- TEST_RR_OP( 9, subw, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 );
- TEST_RR_OP( 10, subw, 0x000000007fff8000, 0x000000007fffffff, 0x0000000000007fff );
-
- TEST_RR_OP( 11, subw, 0x000000007fff8001, 0xffffffff80000000, 0x0000000000007fff );
- TEST_RR_OP( 12, subw, 0xffffffff80007fff, 0x000000007fffffff, 0xffffffffffff8000 );
-
- TEST_RR_OP( 13, subw, 0x0000000000000001, 0x0000000000000000, 0xffffffffffffffff );
- TEST_RR_OP( 14, subw, 0xfffffffffffffffe, 0xffffffffffffffff, 0x0000000000000001 );
- TEST_RR_OP( 15, subw, 0x0000000000000000, 0xffffffffffffffff, 0xffffffffffffffff );
-
- #-------------------------------------------------------------
- # Source/Destination tests
- #-------------------------------------------------------------
-
- TEST_RR_SRC1_EQ_DEST( 16, subw, 2, 13, 11 );
- TEST_RR_SRC2_EQ_DEST( 17, subw, 3, 14, 11 );
- TEST_RR_SRC12_EQ_DEST( 18, subw, 0, 13 );
-
- #-------------------------------------------------------------
- # Bypassing tests
- #-------------------------------------------------------------
-
- TEST_RR_DEST_BYPASS( 19, 0, subw, 2, 13, 11 );
- TEST_RR_DEST_BYPASS( 20, 1, subw, 3, 14, 11 );
- TEST_RR_DEST_BYPASS( 21, 2, subw, 4, 15, 11 );
-
- TEST_RR_SRC12_BYPASS( 22, 0, 0, subw, 2, 13, 11 );
- TEST_RR_SRC12_BYPASS( 23, 0, 1, subw, 3, 14, 11 );
- TEST_RR_SRC12_BYPASS( 24, 0, 2, subw, 4, 15, 11 );
- TEST_RR_SRC12_BYPASS( 25, 1, 0, subw, 2, 13, 11 );
- TEST_RR_SRC12_BYPASS( 26, 1, 1, subw, 3, 14, 11 );
- TEST_RR_SRC12_BYPASS( 27, 2, 0, subw, 4, 15, 11 );
-
- TEST_RR_SRC21_BYPASS( 28, 0, 0, subw, 2, 13, 11 );
- TEST_RR_SRC21_BYPASS( 29, 0, 1, subw, 3, 14, 11 );
- TEST_RR_SRC21_BYPASS( 30, 0, 2, subw, 4, 15, 11 );
- TEST_RR_SRC21_BYPASS( 31, 1, 0, subw, 2, 13, 11 );
- TEST_RR_SRC21_BYPASS( 32, 1, 1, subw, 3, 14, 11 );
- TEST_RR_SRC21_BYPASS( 33, 2, 0, subw, 4, 15, 11 );
-
- TEST_RR_ZEROSRC1( 34, subw, 15, -15 );
- TEST_RR_ZEROSRC2( 35, subw, 32, 32 );
- TEST_RR_ZEROSRC12( 36, subw, 0 );
- TEST_RR_ZERODEST( 37, subw, 16, 30 );
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
diff --git a/tests/riscv-tests/test_macros.h b/tests/riscv-tests/test_macros.h
@@ -707,9 +707,9 @@ test_ ## testnum: \
TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, double val1, double 0, double 0, \
inst a0, f10, rm; li t2, ((result) << 32 >> 63) * -1)
-#define TEST_FP_INT_OP_D( testnum, inst, flags, result, val1, rm ) \
- TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, double val1, double 0, double 0, \
- inst a0, f10, rm)
+/* #define TEST_FP_INT_OP_D( testnum, inst, flags, result, val1, rm ) \
+ TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, double val1, double 0, double 0, \
+ inst a0, f10, rm) */
#define TEST_FP_CMP_OP_S( testnum, inst, flags, result, val1, val2 ) \
TEST_FP_OP_S_INTERNAL( testnum, flags, word result, float val1, float val2, float 0, \
