rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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commit 4bef323217454349b806321de1a4fb30a4374b13
parent 46faf7ecf266867f88dc1b231b59218b96ceabaa
Author: Vineet Kumar <git@vineetk.net>
Date:   Wed,  3 Jun 2026 13:19:14 -0400

use gowin-specific synthesis flow

Diffstat:
MMakefile | 2+-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile @@ -12,7 +12,7 @@ lint: ${PKG_SRC} ${SV_SRCS} ${PKG_SRC} ${SV_SRCS} synth: - yosys -m slang -p 'read_slang ${PKG_SRC} ${SV_SRCS}; synth -top rv32g_hart' + yosys -m slang -p 'read_slang ${PKG_SRC} ${SV_SRCS}; synth_gowin -top rv32g_hart' clean: rm -rf ${OBJDIR}