rv32g-core

commit 46faf7ecf266867f88dc1b231b59218b96ceabaa
parent 752f85caec05a75087f8dec4e2cdab4935ae3661
Author: Vineet Kumar <git@vineetk.net>
Date:   Tue,  2 Jun 2026 22:03:32 -0400

add makefile for linting and synthesis

Diffstat:
A
Makefile
 | 
18
++++++++++++++++++
A
manifest.scm
 | 
6
++++++

2 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/Makefile b/Makefile
@@ -0,0 +1,18 @@
+SRCDIR := rtl
+OBJDIR := obj_dir
+
+PKG_SRC := ${SRCDIR}/rv32g_pkg.sv
+SV_SRCS := ${SRCDIR}/rv32g_hart.sv ${wildcard ${SRCDIR}/stage_*.sv}
+
+all: lint synth
+
+lint: ${PKG_SRC} ${SV_SRCS}
+	verilator --lint-only --timing \
+	    +1800-2023ext+.sv \
+	    ${PKG_SRC} ${SV_SRCS}
+
+synth:
+	yosys -m slang -p 'read_slang ${PKG_SRC} ${SV_SRCS}; synth -top rv32g_hart'
+
+clean:
+	rm -rf ${OBJDIR}
diff --git a/manifest.scm b/manifest.scm
@@ -0,0 +1,6 @@
+(use-modules (gnu packages base)
+	     (gnu packages electronics))
+
+(packages->manifest (list gnu-make
+			  verilator
+			  yosys))