commit 4d57607f9897c3f96812d96bae95427f3f24d361
parent b2f619d2772cb7e6a9f951d15cd6d4fda3b27f76
Author: Vineet Kumar <git@vineetk.net>
Date: Sun, 12 Jul 2026 15:05:11 +0530
fix readme's claim about zicsr+mret having identical performance and usage
Diffstat:
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/README.org b/README.org
@@ -64,9 +64,8 @@ run on it. I may change my mind regarding this later on.
- Without instruction memory cache: ~40.5 MHz, 15.8k LUT4
- With instruction memory cache: ~33.9 MHz, 24.1k LUT4
- July 8, 2026: Zicsr and PRIV-MRET Completed
- - clock speed and LUT4s after PnR (cache_depth=4096):
- - With instruction memory cache: ~33.9 MHz, 24.1k LUT4
- - this shows the extra CSR registers had a negligible effect
+ - clock speed and LUT4s after PnR (cache_depth=64):
+ - With instruction memory cache: ~40.3 MHz, 154.7k LUT4, 8440 RAM16SDP4
- July 12, 2026: Basic 5-stage Pipeline Completed
- clock speed and LUT4s after PnR (cache_depth=8192)
- With instruction memory cache: ~203.9 MHz, 929 LUT4, 8 RAM16SDP4, 1 BSRAM
