rv32g-core

commit b2f619d2772cb7e6a9f951d15cd6d4fda3b27f76
parent e47093efc32ef69a2bdc66a837d437e1958bd158
Author: Vineet Kumar <git@vineetk.net>
Date:   Sun, 12 Jul 2026 12:16:23 +0530

fix csr regfile memory inference

Diffstat:
M
README.org
 | 
4
++++
M
rtl/rv32g_hart.sv
 | 
4
++++
M
rtl/rv32g_hart_top.sv
 | 
3
++-
M
rtl/rv32g_pkg.sv
 | 
2
+-
M
rtl/tb_rv32g.sv
 | 
6
++++--

5 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/README.org b/README.org
@@ -67,6 +67,10 @@ run on it. I may change my mind regarding this later on.
   - clock speed and LUT4s after PnR (cache_depth=4096):
     - With instruction memory cache: ~33.9 MHz, 24.1k LUT4
     - this shows the extra CSR registers had a negligible effect
+- July 12, 2026: Basic 5-stage Pipeline Completed
+  - clock speed and LUT4s after PnR (cache_depth=8192)
+    - With instruction memory cache: ~203.9 MHz, 929 LUT4, 8 RAM16SDP4, 1 BSRAM
+
 * Resources Used
 - [[https://docs.riscv.org/reference/isa/_attachments/riscv-unprivileged.pdf][RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture (Version
   20260120)]]
diff --git a/rtl/rv32g_hart.sv b/rtl/rv32g_hart.sv
@@ -14,6 +14,8 @@ module rv32g_hart
     output logic	dmem_we,
     output logic [3:0]	dmem_be,
 
+    output reg_t	pc_out,
+
     output exception_t	exception);
 
    // x0 to x31
@@ -51,6 +53,8 @@ module rv32g_hart
    logic [31:0]	fetch_inst;
    reg_t	pc_reg;
    
+   assign pc_out = pc_reg;
+
    stage_fetch u_fetch(.clk, .rstN, .flush_i(idex_reg.ctrl.fence_flush), .pc(pc_reg), .imem_addr, .imem_data, .inst(fetch_inst));
    // IF/ID pipeline register
    always_comb begin
diff --git a/rtl/rv32g_hart_top.sv b/rtl/rv32g_hart_top.sv
@@ -15,6 +15,7 @@ module rv32g_hart_top
    logic [31:0]	dmem_rdata;
    logic [31:0]	dmem_wdata;
    logic	dmem_valid; // now driven by memory
+   reg_t	pc_out;
 
    // Instantiate unified memory (modified to output dmem_valid)
    unified_memory u_mem (.clk, .imem_addr, .imem_data, .imem_valid,
@@ -22,7 +23,7 @@ module rv32g_hart_top
 			 .dmem_wdata, .dmem_rdata, .dmem_valid);
 
    // Instantiate the core
-   rv32g_hart dut (.clk, .rstN, .exception,
+   rv32g_hart dut (.clk, .rstN, .pc_out, .exception,
 		   .imem_addr, .imem_data, .imem_valid,
 		   .dmem_addr, .dmem_valid,
 		   .dmem_rdata, .dmem_wdata,
diff --git a/rtl/rv32g_pkg.sv b/rtl/rv32g_pkg.sv
@@ -169,7 +169,7 @@ package rv32g_pkg;
 			     WB_IMM   // LUI writes back an immediate value
 			     } wbsrc_t;
 
-   localparam CSR_SIZE = 40;
+   localparam CSR_SIZE = 64;
    typedef enum logic [2:0] {CSR_NONE,
 			     CSR_RW,
 			     CSR_RS,
diff --git a/rtl/tb_rv32g.sv b/rtl/tb_rv32g.sv
@@ -21,6 +21,8 @@ module tb_rv32g
    logic [31:0]	dmem_wdata;
    logic	dmem_valid;
 
+   reg_t	pc_out;
+
    exception_t	exception;
 
    string	rom_filename;
@@ -64,7 +66,7 @@ module tb_rv32g
 			 .dmem_addr, .dmem_we, .dmem_be, .dmem_valid,
 			 .dmem_wdata, .dmem_rdata);
 
-   rv32g_hart dut(.clk, .rstN, .exception,
+   rv32g_hart dut(.clk, .rstN, .pc_out, .exception,
 		  .imem_addr, .imem_data, .imem_valid,
 		  .dmem_addr, .dmem_valid,
 		  .dmem_rdata, .dmem_wdata,
@@ -81,7 +83,7 @@ module tb_rv32g
    parameter int MAX_CYCLES = 10000;
    always_ff @(posedge clk) begin
      if (exception == EXC_ILL_INST && seen_first_real_inst) begin
-       $display("!!! Program terminated (exception ILL_INST at PC %h) !!!", dut.idex_reg.pc);
+       $display("!!! Program terminated (exception ILL_INST at PC %h) !!!", pc_out);
        $finish();
      end