rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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commit 6f52fe98d857ebe9298a5cf2dbd729f6c129247b
parent 43306a63fb75f3320de54b7909f6d2003cd1872a
Author: Vineet Kumar <git@vineetk.net>
Date:   Tue,  2 Jun 2026 14:58:48 -0400

add .gitignore

Diffstat:

A.gitignore | 2++


1 file changed, 2 insertions(+), 0 deletions(-)

diff --git a/.gitignore b/.gitignore
@@ -0,0 +1,2 @@
+#*
+obj_dir