commit 7265302587f4476b0746d5f3a682f4108b284ae4
parent 96ed6dba8e30b9ae0fc2758d6ac7fd7ff59d56ba
Author: Vineet Kumar <git@vineetk.net>
Date: Sat, 22 Aug 2026 05:16:35 +0530
update README with current milestone
I unfortunately could not work on this as much as I'd have liked over
this summer :(
Recovery-Origin: 9433c749371ec6e67e38404e4735f101da1fa9e3
Recovery-Status: reconstructed history
Complete final source tree is exact: every path, mode and blob matches original August22 tree dc03c2fb4d5e24ec4aedb7c18b8889b7bb2769a4. Original parent history is reconstructed, so this new commit has a different ID.
Diffstat:
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/README.org b/README.org
@@ -28,7 +28,7 @@ run on it. I may change my mind regarding this later on.
*** Architecture Progress
1. Single-cycle RV32I (DONE)
-2. 5-stage pipeline (in progress)
+2. 5-stage pipeline (DONE)
3. Zicsr and Zifencei (partial)
4. M and A extensions
5. 6/7-stage pipeline
@@ -66,6 +66,13 @@ run on it. I may change my mind regarding this later on.
- July 8, 2026: Zicsr and PRIV-MRET Completed
- clock speed and LUT4s after PnR (cache_depth=64):
- With instruction memory cache: ~40.3 MHz, 154.7k LUT4, 8440 RAM16SDP4
+- August 6, 2026: Preliminary 5-stage Pipelining Completed
+ - clock speed and LUT4s after PnR (cache_depth=8192):
+ - With I-cache: ~75.2 MHz, 3.9k LUT4, 32 RAM16SDP4, 34 BSRAM
+ - Without I-cache: ~96.7 MHz, 2.2k LUT4, 32 RAM16SDP4, 32 BSRAM
+- August 22, 2026: Proper 5-stage Pipelining Completed
+ - clock speed and LUT4s after PnR (cache_depth=8192):
+ - With I-cache: ~100.2 MHz, 2.3k LUT4, 32 RAM16SDP4, 32 BSRAM
* Resources Used
- [[https://docs.riscv.org/reference/isa/_attachments/riscv-unprivileged.pdf][RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture (Version
