rv32g-core

commit 752f85caec05a75087f8dec4e2cdab4935ae3661
parent 6f52fe98d857ebe9298a5cf2dbd729f6c129247b
Author: Vineet Kumar <git@vineetk.net>
Date:   Tue,  2 Jun 2026 21:54:39 -0400

fix synthesis issues

Diffstat:
M
rtl/rv32g_hart.sv
 | 
15
+++++++++------
M
rtl/stage_decode.sv
 | 
4
++--

2 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/rtl/rv32g_hart.sv b/rtl/rv32g_hart.sv
@@ -29,11 +29,12 @@ module rv32g_hart
    reg_t	mem_out;
    logic	branch_taken;
    
-   always_ff @(posedge clk or negedge rstN) begin
-     if (!rstN) begin
-       for (int i = 0; i < 32; i++) regfile[i] <= '0;
-     end
-   end
+   // FIXME slang complains about async sensitivity. can be removed if writeback's same reset has no issue.
+   // always_ff @(posedge clk or negedge rstN) begin
+   //   if (!rstN) begin
+   //     for (int i = 0; i < 32; i++) regfile[i] <= '0;
+   //   end
+   // end
 
    stage_fetch u_fetch(.pc, .imem_addr, .imem_data, .inst);
 
@@ -70,7 +71,9 @@ module rv32g_hart
    // TODO EX/MEM pipeline register
    always_ff @(posedge clk or negedge rstN) begin
      if (!rstN) ; // TODO reset pipeline register
-     else if (!dmem_valid && ctrl.memop != MEM_NONE) ; // TODO stall
+     else if (!dmem_valid && ctrl.memop != MEM_NONE) begin
+       // TODO stall
+     end
    end
    // TODO stall when dmem_valid is 0 and ctrl.memop != 0. find out what else needs to be done in between stages
    
diff --git a/rtl/stage_decode.sv b/rtl/stage_decode.sv
@@ -43,9 +43,9 @@ module stage_decode
      unique case (inst_type)
        ITYPE: imm = {{20{inst[31]}}, inst[31:20]};
        STYPE: imm = {{20{inst[31]}}, inst[31:25], inst[11:7]};
-       BTYPE: imm = {{20{inst[31]}}, inst[7], inst[30:25], inst[11:8], '0};
+       BTYPE: imm = {{20{inst[31]}}, inst[7], inst[30:25], inst[11:8], 1'b0};
        UTYPE: imm = inst[31:12] << 12;
-       JTYPE: imm = {{12{inst[31]}}, inst[19:12], inst[20], inst[30:25], inst[24:21], '0};
+       JTYPE: imm = {{12{inst[31]}}, inst[19:12], inst[20], inst[30:25], inst[24:21], 1'b0};
        default: imm = '0;
      endcase
    end