rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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commit 79c6c61d54ef8b96ed8395845ac1d08e84f9c304
parent f48d239dd38f14746d5a9affcc4cb5122e692eeb
Author: Vineet Kumar <git@vineetk.net>
Date:   Wed, 10 Jun 2026 14:41:44 -0400

check if pass and fail functions exist in test, print if not

Diffstat:
MMakefile | 4+++-
1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Makefile b/Makefile @@ -46,7 +46,9 @@ $(TEST_DIR)/%.pass: $(TEST_DIR)/%.hex sim_compile @pass=$$(readelf -s $(basename $<) | awk '/pass$$/ {print $$2}'); \ fail=$$(readelf -s $(basename $<) | awk '/fail$$/ {print $$2}'); \ $(SIM) +rom=$< > $(LOG_DIR)/$*.log; \ - if grep -q "^IF: pc: $$fail" $(LOG_DIR)/$*.log; then \ + if ! $$(readelf -s $(basename $<) | grep -qE 'pass|fail'); then \ + echo "pass and fail functions not found"; \ + elif grep -q "^IF: pc: $$fail" $(LOG_DIR)/$*.log; then \ echo "fail"; \ elif grep -q "^IF: pc: $$pass" $(LOG_DIR)/$*.log; then \ echo "pass"; \