rv32g-core

commit f48d239dd38f14746d5a9affcc4cb5122e692eeb
parent dce248adc7f59090c3035d6d395da4c0f9bbef72
Author: Vineet Kumar <git@vineetk.net>
Date:   Tue,  9 Jun 2026 20:20:00 -0400

fix shamt to be combinational assign, not initial

same logic error as a previous commit for a different instruction

Diffstat:
M
rtl/stage_execute.sv
 | 
4
+++-

1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/rtl/stage_execute.sv b/rtl/stage_execute.sv
@@ -13,7 +13,7 @@ module stage_execute
 
    reg_t a;
    reg_t b;
-   logic [4:0] shamt = b[4:0];
+   logic [4:0] shamt;
 
    always_comb begin
      // assign inputs
@@ -28,6 +28,8 @@ module stage_execute
        ALUOP2_IMM: b = imm;
      endcase
 
+     shamt = b[4:0];
+
      // perform computation
      unique case (op)
        ALU_NONE: out = '0;