rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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commit c0570886bd05ba4405a31e00b4140b46150202e1
parent d9c131d821c269835722e634cf8dca7529f811dc
Author: Vineet Kumar <git@vineetk.net>
Date:   Wed, 10 Jun 2026 21:20:54 -0400

temporarily decrease cache depth to 64 words

Diffstat:
Mrtl/rv32g_pkg.sv | 3++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/rtl/rv32g_pkg.sv b/rtl/rv32g_pkg.sv @@ -1,6 +1,7 @@ package rv32g_pkg; parameter BASE_ADDR = 32'h8000_0000; - parameter CACHE_DEPTH = 4096; + //parameter CACHE_DEPTH = 4096; + parameter CACHE_DEPTH = 64; typedef logic [31:0] reg_t;