rv32g-core

commit d9c131d821c269835722e634cf8dca7529f811dc
parent 5f15f69a4fa7550162b0f666e55801e102168c3d
Author: Vineet Kumar <git@vineetk.net>
Date:   Wed, 10 Jun 2026 21:11:00 -0400

add pnr makefile target

Diffstat:
M
Makefile
 | 
7
+++++++
M
manifest.scm
 | 
1
+

2 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/Makefile b/Makefile
@@ -5,6 +5,10 @@ PKG_SRC   := ${SRCDIR}/rv32g_pkg.sv
 TB_SRC    := ${SRCDIR}/tb_rv32g.sv
 SV_SRCS   := ${SRCDIR}/rv32g_hart.sv ${wildcard ${SRCDIR}/stage_*.sv} ${SRCDIR}/unified_memory.sv
 TOP_SRC   := ${SRCDIR}/rv32g_hart_top.sv
+CST_SRC   := ${SRCDIR}/rv32g_hart_top.cst
+
+#NEXTPNR_DEV := GW5A-LV25MG121NES
+NEXTPNR_DEV := GW5AST-LV138PG484AC1/I0
 
 # tests
 TEST_DIR   := tests/riscv-tests/isa
@@ -28,6 +32,9 @@ lint: $(PKG_SRC) $(SV_SRCS)
 synth:
 	yosys -m slang -p 'read_slang $(PKG_SRC) $(SV_SRCS) $(TOP_SRC); synth_gowin -family gw5a -top rv32g_hart_top -json design.json'
 
+pnr:
+	nextpnr-himbaechel-gowin --json design.json --write design_pnr.json --freq 300 --device ${NEXTPNR_DEV} --vopt cst=${CST_SRC}
+
 sim_compile: lint $(PKG_SRC) $(TB_SRC) $(SV_SRCS)
 	verilator --binary --exe --build --timing \
 	    --top tb_rv32g \
diff --git a/manifest.scm b/manifest.scm
@@ -6,6 +6,7 @@
 
 (packages->manifest (list gcc-toolchain
 			  gnu-make
+			  nextpnr-cli
 			  python
 			  verilator
 			  yosys