rv32g-core

commit e8a42ce6ad99bde0c0194a25f4dcc33d94de1895
parent dd1ae9ee4aa0872f82646e895d2a79df07cdff8d
Author: Vineet Kumar <git@vineetk.net>
Date:   Mon,  8 Jun 2026 14:52:58 -0400

output better logging

Diffstat:
M
rtl/rv32g_hart.sv
 | 
19
++++++++++++++-----
M
rtl/stage_decode.sv
 | 
3
+++

2 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/rtl/rv32g_hart.sv b/rtl/rv32g_hart.sv
@@ -37,9 +37,8 @@ module rv32g_hart
    // end
 
    stage_fetch u_fetch(.pc, .imem_addr, .imem_data, .inst);
-
    always_ff @(posedge clk or negedge rstN) begin
-     $display("PC: %h, Next PC: %h, rstN: %d, imem_valid: %d, imem_data: %h", pc, next_pc, rstN, imem_valid, imem_data);
+     $display("IF:  pc: %h, next_pc: %h, imem_valid: %d, imem[%h]: %h, inst: %h", pc, next_pc, imem_valid, imem_addr, imem_data, inst);
      if (!rstN) pc <= '0;
      else if (imem_valid) pc <= next_pc;
      else begin
@@ -50,14 +49,15 @@ module rv32g_hart
    stage_decode u_decode(.inst, .regfile, .ctrl, .imm, .rs1_val, .rs2_val, .rd_num);
    // TODO ID/EX pipeline register
    always_ff @(posedge clk or negedge rstN) begin
+     $display("ID:  inst: %h, ctrl: %h, imm: %h, rs1_val: %h, rs2_val: %h, rd_num: %d", inst, ctrl, imm, rs1_val, rs2_val, rd_num);
      if (!rstN) ; // TODO reset pipeline register
      else if (ctrl.exception != EXC_NONE) begin
        // TODO handle exceptions
        unique case (ctrl.exception)
 	 EXC_NONE: ;
-	 EXC_ILL_INST: ;
-	 EXC_CALL: ;
-	 EXC_BKPT: ;
+	 EXC_ILL_INST: $display("Exception: illegal instruction, inst: %h", inst);
+	 EXC_CALL: $display("Exception: ECALL");
+	 EXC_BKPT: $display("Exception: BREAK");
        endcase
      end
    end
@@ -71,6 +71,7 @@ module rv32g_hart
 			   .imm, .pc, .rs1_val, .rs2_val, .branch_taken);
    // TODO EX/MEM pipeline register
    always_ff @(posedge clk or negedge rstN) begin
+     $display("EX:  op: %h, op1src: %d, op2src: %d, branchop: %d, out: %h, branch_taken: %d", ctrl.aluop, ctrl.aluop1src, ctrl.aluop2src, ctrl.branchop, alu_out, branch_taken);
      if (!rstN) ; // TODO reset pipeline register
      else if (!dmem_valid && ctrl.memop != MEM_NONE) begin
        // TODO stall
@@ -81,10 +82,18 @@ module rv32g_hart
    stage_memory u_mem(.memop(ctrl.memop), .alu_out, .rs2_val,
 		      .dmem_addr, .dmem_data, .dmem_wdata, .dmem_we, .dmem_be, .mem_out);
    // TODO MEM/WB pipeline register
+   always_ff @(posedge clk or negedge rstN) begin
+     $display("MEM: memop: %h, dmem_addr: %h, dmem_data: %h, dmem_wdata: %h, dmem_we: %d, dmem_be: %b, mem_out: %h", ctrl.memop, dmem_addr, dmem_data, dmem_wdata, dmem_we, dmem_be, mem_out);
+     if (!rstN) ; // TODO reset pipeline register
+     else ; // TODO I need to think of what else should happen
+   end
    // TODO find out what else needs to be done in between stages
 
    stage_writeback u_wb(.clk, .rstN, .wbsrc(ctrl.wbsrc), .rd_num, .regfile,
 			.pc, .imm, .alu_out, .mem_out);
+   always_ff @(posedge clk) begin
+     $display("WB:  wbsrc: %d, rd_num: %d, pc: %h, imm: %h, alu_out: %h, mem_out: %h", ctrl.wbsrc, rd_num, pc, imm, alu_out, mem_out);
+   end
    // TODO find out what else needs to be done after this stage
 
    always_comb begin
diff --git a/rtl/stage_decode.sv b/rtl/stage_decode.sv
@@ -119,6 +119,9 @@ module stage_decode
 	      branchop:  BRANCH_NONE,
 	      wbsrc:     WB_NONE,
 	      exception: EXC_NONE};
+
+     $display("inst[6:0]: %b, opcode: %b %s", inst[6:0], opcode, opcode.name());
+
      // the major opcodes share the same signals, just operation varies based on funct
      unique case (opcode)
        OPCODE_LUI: ctrl.wbsrc = WB_IMM;