commit ff697575ef55ed75410e7966dd0db8e57b073162
parent 419dcb72107c7fcea7695bed6d722bc8a6921b44
Author: Vineet Kumar <git@vineetk.net>
Date: Fri, 12 Jun 2026 00:42:02 -0400
update readme with current progress
Diffstat:
1 file changed, 20 insertions(+), 4 deletions(-)
diff --git a/README.org b/README.org
@@ -27,14 +27,14 @@ run on it. I may change my mind regarding this later on.
- Zifencei (Instruction-Fetch Fence)
*** Architecture Progress
-1. Single-cycle RV32I
-2. 5-stage pipeline
-3. Zicsr and Zifencei
+1. Single-cycle RV32I (DONE)
+2. 5-stage pipeline (in progress)
+3. Zicsr and Zifencei (partial)
4. M and A extensions
5. 6/7-stage pipeline
6. Branch prediction
7. F and D extensions
-8. SRAM caching
+8. SRAM caching (partial)
9. SDRAM controller
** Target Platforms
@@ -48,6 +48,22 @@ run on it. I may change my mind regarding this later on.
- Would start tapeout of it after all goals met and using it faces no issues
with FPGA
+* Milestones
+- June 11, 2026: Single-Cycle RV32I-Zifencei Completed
+ - all tests pass (except rv32ui-p-ma_data which tests misaligned accesses)
+ - no misaligned memory accesses because it's complicated to do in
+ single-cycle hardware due to needing multiple memory accesses
+ - major problem is that due to memory accesses needing to be combinational
+ (within single cycle), it forces memory and cache data to be in distributed
+ RAM (RAM16SDP4 on GoWin) and cache tags in LUTs, so synthesized memory
+ cannot be large unlike in simulation
+ - critical path dominated by this causing unoptimal routing and large number
+ of cells
+ - clock speed and LUT4s after PnR (cache_depth=64 so arc routing doesn't takes
+ hours):
+ - Without instruction memory cache: ~40.5 MHz, 15.8k LUT4
+ - With instruction memory cache: ~33.9 MHz, 24.1k LUT4
+
* Resources Used
- [[https://docs.riscv.org/reference/isa/_attachments/riscv-unprivileged.pdf][RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture (Version
20260120)]]
