rv32g-core

commit 419dcb72107c7fcea7695bed6d722bc8a6921b44
parent 84f8e967e9967417469d344beba129e4d2cc21aa
Author: Vineet Kumar <git@vineetk.net>
Date:   Fri, 12 Jun 2026 00:41:13 -0400

add librelane

Diffstat:
M
.gitignore
 | 
1
+
A
librelane.json
 | 
15
+++++++++++++++
M
manifest.scm
 | 
1
+

3 files changed, 17 insertions(+), 0 deletions(-)
diff --git a/.gitignore b/.gitignore
@@ -4,3 +4,4 @@ tests/.test_list
 design.json
 design_pnr.json
 *.rpt
+runs/
diff --git a/librelane.json b/librelane.json
@@ -0,0 +1,15 @@
+{
+    "DESIGN_NAME": "rv32g_hart_top",
+    "VERILOG_FILES": ["dir::rtl/rv32g_pkg.sv",
+		      "dir::rtl/rv32g_hart.sv",
+		      "dir::rtl/stage_decode.sv",
+		      "dir::rtl/stage_execute.sv",
+		      "dir::rtl/stage_fetch.sv",
+		      "dir::rtl/stage_memory.sv",
+		      "dir::rtl/stage_writeback.sv",
+		      "dir::rtl/unified_memory.sv",
+		      "dir::rtl/rv32g_hart_top.sv"],
+    "CLOCK_PERIOD": 250,
+    "CLOCK_PORT": "clk",
+    "USE_SLANG": true
+}
diff --git a/manifest.scm b/manifest.scm
@@ -6,6 +6,7 @@
 
 (packages->manifest (list gcc-toolchain
 			  gnu-make
+			  librelane
 			  nextpnr-cli
 			  python
 			  verilator