commit fe9f4859cde2e57a482a8af26275e659bcf6f6c7
parent 26ae3798b9234e981551a99392e5dcd1ada184bf
Author: Vineet Kumar <git@vineetk.net>
Date: Tue, 4 Aug 2026 15:41:02 +0530
vendor riscv-tests with using result address instead of zicsr
also makes it easy for me to find out if a test actually finished
instead of inferring based on PC
Diffstat:
109 files changed, 8497 insertions(+), 17 deletions(-)
diff --git a/rtl/tb_rv32g.sv b/rtl/tb_rv32g.sv
@@ -4,6 +4,8 @@ module tb_rv32g
import rv32g_pkg::*;
();
+ localparam RESULT_ADDR = 'h80004ffc;
+
// DUT (design-under-test) ports
logic clk;
logic rstN;
@@ -105,11 +107,14 @@ module tb_rv32g
endcase
end
- // if (exception == EXC_ILL_INST && seen_first_real_inst) begin
- // $display("!!! Program terminated (exception ILL_INST at PC %h), inst: %h !!!",
- // pc_out, dut.ifid_reg.inst);
- // $finish();
- // end
+ // this is how I'm doing pass and fails for tests
+ if (exception == EXC_CALL) begin
+ $display("+++ %s: pass (%0d cycles) +++", rom_filename, cycle_cnt);
+ $finish();
+ end else if (exception == EXC_BKPT) begin
+ $display("+++ %s: fail (test %0d, %0d cycles) +++", rom_filename, dut.regfile[3], cycle_cnt);
+ $finish();
+ end
if (exception == EXC_ILL_INST && seen_first_real_inst && dut.ifid_reg.inst == 32'b0) begin
$display("!!! Program terminated (exception ILL_INST at PC %h), inst: %h !!!",
diff --git a/tests/elf2hex b/tests/elf2hex
@@ -1,12 +0,0 @@
-#!/bin/sh
-riscv32-unknown-elf-objcopy -O verilog --verilog-data-width=4 "${1}" file.bin;
-awk '
- /^@/ {
- base = 0x20000000
- addr = strtonum("0x" substr($0,2))
- idx = addr - base
- printf "@%X\n", idx
- next
- }
- { gsub(/ /, "\n"); print }' file.bin >"${1}".hex
-rm file.bin
diff --git a/tests/riscv-tests/link.ld b/tests/riscv-tests/link.ld
@@ -0,0 +1,18 @@
+OUTPUT_ARCH( "riscv" )
+ENTRY(_start)
+
+SECTIONS
+{
+ /* . = 0x80000000; */
+ . = 0x00000000;
+ .text.init : { *(.text.init) }
+ . = ALIGN(0x1000);
+ .tohost : { *(.tohost) }
+ . = ALIGN(0x1000);
+ .text : { *(.text) }
+ . = ALIGN(0x1000);
+ .data : { *(.data) }
+ .bss : { *(.bss) }
+ _end = .;
+}
+
diff --git a/tests/riscv-tests/riscv_test.h b/tests/riscv-tests/riscv_test.h
@@ -0,0 +1,110 @@
+// See LICENSE for license details.
+
+#ifndef _ENV_PHYSICAL_SINGLE_CORE_H
+#define _ENV_PHYSICAL_SINGLE_CORE_H
+
+//-----------------------------------------------------------------------
+// Begin Macro
+//-----------------------------------------------------------------------
+
+#define RESULT_ADDR 0x80004ffc
+
+#define RVTEST_RV32U \
+ .macro init; \
+ .endm
+#define RVTEST_RV64U RVTEST_RV32U
+
+#define RVTEST_RV32UF \
+ .macro init; \
+ RVTEST_FP_ENABLE; \
+ .endm
+#define RVTEST_RV64UF RVTEST_RV32UF
+#define TEST_FP_INT_OP_D TEST_FP_INT_OP_D32
+
+#define RVTEST_RV32UV \
+ .macro init; \
+ RVTEST_VECTOR_ENABLE; \
+ .endm
+#define RVTEST_RV64UV RVTEST_RV32UV
+
+#define CHECK_XLEN li a0, 1; slli a0, a0, 31; bltz a0, 1f; RVTEST_PASS; 1:
+
+#define INIT_XREG \
+ li x1, 0; \
+ li x2, 0; \
+ li x3, 0; \
+ li x4, 0; \
+ li x5, 0; \
+ li x6, 0; \
+ li x7, 0; \
+ li x8, 0; \
+ li x9, 0; \
+ li x10, 0; \
+ li x11, 0; \
+ li x12, 0; \
+ li x13, 0; \
+ li x14, 0; \
+ li x15, 0; \
+ li x16, 0; \
+ li x17, 0; \
+ li x18, 0; \
+ li x19, 0; \
+ li x20, 0; \
+ li x21, 0; \
+ li x22, 0; \
+ li x23, 0; \
+ li x24, 0; \
+ li x25, 0; \
+ li x26, 0; \
+ li x27, 0; \
+ li x28, 0; \
+ li x29, 0; \
+ li x30, 0; \
+ li x31, 0;
+
+#define RVTEST_CODE_BEGIN \
+ .section .text.init; \
+ .align 2; \
+ .globl _start; \
+_start: \
+ INIT_XREG; \
+ li TESTNUM, 0; \
+ init; \
+1:
+
+//-----------------------------------------------------------------------
+// End Macro
+//-----------------------------------------------------------------------
+
+#define RVTEST_CODE_END \
+ unimp
+
+//-----------------------------------------------------------------------
+// Pass/Fail Macro
+//-----------------------------------------------------------------------
+
+#define RVTEST_PASS \
+ fence; \
+1: li TESTNUM, 1; \
+ li x31, RESULT_ADDR; \
+ sw TESTNUM, 0(x31); \
+ ecall;
+
+
+#define TESTNUM gp
+#define RVTEST_FAIL \
+ fence; \
+1: beqz TESTNUM, 1b; \
+ slli TESTNUM, TESTNUM, 1; \
+ ori TESTNUM, TESTNUM, 1; \
+ sw TESTNUM, 0(x31); \
+ ebreak
+
+//-----------------------------------------------------------------------
+// Data Section Macro
+//-----------------------------------------------------------------------
+
+#define RVTEST_DATA_BEGIN .align 4;
+#define RVTEST_DATA_END .align 4;
+
+#endif
diff --git a/tests/riscv-tests/rv32ua/amoadd_d.S b/tests/riscv-tests/rv32ua/amoadd_d.S
@@ -0,0 +1,47 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoadd_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amoadd.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0xffffffff80000000, \
+ li a0, 0xffffffff80000000; \
+ li a1, 0xfffffffffffff800; \
+ la a3, amo_operand; \
+ sd a0, 0(a3); \
+ amoadd.d a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0xffffffff7ffff800, ld a5, 0(a3))
+
+ # try again after a cache miss
+ TEST_CASE(4, a4, 0xffffffff7ffff800, \
+ amoadd.d a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0xffffffff7ffff000, ld a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
diff --git a/tests/riscv-tests/rv32ua/amoadd_w.S b/tests/riscv-tests/rv32ua/amoadd_w.S
@@ -0,0 +1,48 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoadd_w.S
+#-----------------------------------------------------------------------------
+#
+# Test amoadd.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0xffffffff80000000, \
+ li a0, 0xffffffff80000000; \
+ li a1, 0xfffffffffffff800; \
+ la a3, amo_operand; \
+ sw a0, 0(a3); \
+ amoadd.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0x000000007ffff800, lw a5, 0(a3))
+
+ # try again after a cache miss
+ TEST_CASE(4, a4, 0x000000007ffff800, \
+ li a1, 0xffffffff80000000; \
+ amoadd.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0xfffffffffffff800, lw a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
diff --git a/tests/riscv-tests/rv32ua/amoand_d.S b/tests/riscv-tests/rv32ua/amoand_d.S
@@ -0,0 +1,48 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoand_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amoand.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0xffffffff80000000, \
+ li a0, 0xffffffff80000000; \
+ li a1, 0xfffffffffffff800; \
+ la a3, amo_operand; \
+ sd a0, 0(a3); \
+ amoand.d a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3))
+
+ # try again after a cache miss
+ TEST_CASE(4, a4, 0xffffffff80000000, \
+ li a1, 0x0000000080000000; \
+ amoand.d a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0x0000000080000000, ld a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
diff --git a/tests/riscv-tests/rv32ua/amoand_w.S b/tests/riscv-tests/rv32ua/amoand_w.S
@@ -0,0 +1,48 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoand.w.S
+#-----------------------------------------------------------------------------
+#
+# Test amoand.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0xffffffff80000000, \
+ li a0, 0xffffffff80000000; \
+ li a1, 0xfffffffffffff800; \
+ la a3, amo_operand; \
+ sw a0, 0(a3); \
+ amoand.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3))
+
+ # try again after a cache miss
+ TEST_CASE(4, a4, 0xffffffff80000000, \
+ li a1, 0x0000000080000000; \
+ amoand.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0xffffffff80000000, lw a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
diff --git a/tests/riscv-tests/rv32ua/amomax_d.S b/tests/riscv-tests/rv32ua/amomax_d.S
@@ -0,0 +1,48 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amomax_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amomax.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0xffffffff80000000, \
+ li a0, 0xffffffff80000000; \
+ li a1, 0xfffffffffffff800; \
+ la a3, amo_operand; \
+ sd a0, 0(a3); \
+ amomax.d a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3))
+
+ TEST_CASE(4, a4, 0, \
+ li a1, 1; \
+ sd x0, 0(a3); \
+ amomax.d a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 1, ld a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
diff --git a/tests/riscv-tests/rv32ua/amomax_w.S b/tests/riscv-tests/rv32ua/amomax_w.S
@@ -0,0 +1,58 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amomax_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amomax.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0xffffffff80000000, \
+ li a0, 0xffffffff80000000; \
+ li a1, 0xfffffffffffff800; \
+ la a3, amo_operand; \
+ sw a0, 0(a3); \
+ amomax.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3))
+
+ TEST_CASE(4, a4, 0, \
+ li a1, 1; \
+ sw x0, 0(a3); \
+ amomax.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 1, lw a5, 0(a3))
+
+ TEST_CASE(6, a4, 1, \
+ li a0, 0x0000000000000001; \
+ li a1, 0x0000000080000000; \
+ la a3, amo_operand; \
+ sw a0, 0(a3); \
+ amomax.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(7, a5, 1, lw a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
diff --git a/tests/riscv-tests/rv32ua/amomaxu_d.S b/tests/riscv-tests/rv32ua/amomaxu_d.S
@@ -0,0 +1,48 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amomaxu_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amomaxu.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0xffffffff80000000, \
+ li a0, 0xffffffff80000000; \
+ li a1, 0xfffffffffffff800; \
+ la a3, amo_operand; \
+ sd a0, 0(a3); \
+ amomaxu.d a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3))
+
+ TEST_CASE(4, a4, 0, \
+ li a1, 0xffffffffffffffff; \
+ sd x0, 0(a3); \
+ amomaxu.d a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0xffffffffffffffff, ld a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
diff --git a/tests/riscv-tests/rv32ua/amomaxu_w.S b/tests/riscv-tests/rv32ua/amomaxu_w.S
@@ -0,0 +1,62 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amomaxu_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amomaxu.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0xffffffff80000000, \
+ li a0, 0xffffffff80000000; \
+ li a1, 0xfffffffffffff800; \
+ la a3, amo_operand; \
+ sw a0, 0(a3); \
+ amomaxu.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3))
+
+ TEST_CASE(4, a4, 0, \
+ li a1, 0xffffffffffffffff; \
+ sw x0, 0(a3); \
+ amomaxu.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0xffffffffffffffff, lw a5, 0(a3))
+
+ # The following two cases check that the upper 32 bits are ignored on rv64
+ # implementations. Only enable them for rv64.
+ #if __riscv_xlen == 64
+ TEST_CASE(6, a4, 1, \
+ li a0, 0x0000000000000001; \
+ li a1, 0x8000000000000000; \
+ la a3, amo_operand; \
+ sw a0, 0(a3); \
+ amomaxu.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(7, a5, 1, lw a5, 0(a3))
+ #endif
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
diff --git a/tests/riscv-tests/rv32ua/amomin_d.S b/tests/riscv-tests/rv32ua/amomin_d.S
@@ -0,0 +1,48 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amomin_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amomin.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0xffffffff80000000, \
+ li a0, 0xffffffff80000000; \
+ li a1, 0xfffffffffffff800; \
+ la a3, amo_operand; \
+ sd a0, 0(a3); \
+ amomin.d a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3))
+
+ TEST_CASE(4, a4, 0, \
+ li a1, 0xffffffffffffffff; \
+ sd x0, 0(a3); \
+ amomin.d a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0xffffffffffffffff, ld a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
diff --git a/tests/riscv-tests/rv32ua/amomin_w.S b/tests/riscv-tests/rv32ua/amomin_w.S
@@ -0,0 +1,58 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amomin_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amomin.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0xffffffff80000000, \
+ li a0, 0xffffffff80000000; \
+ li a1, 0xfffffffffffff800; \
+ la a3, amo_operand; \
+ sw a0, 0(a3); \
+ amomin.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3))
+
+ TEST_CASE(4, a4, 0, \
+ li a1, 0xffffffffffffffff; \
+ sw x0, 0(a3); \
+ amomin.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0xffffffffffffffff, lw a5, 0(a3))
+
+ TEST_CASE(6, a4, 1, \
+ li a0, 0x0000000000000001; \
+ li a1, 0x0000000080000000; \
+ la a3, amo_operand; \
+ sw a0, 0(a3); \
+ amomin.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(7, a5, 0xffffffff80000000, lw a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
diff --git a/tests/riscv-tests/rv32ua/amominu_d.S b/tests/riscv-tests/rv32ua/amominu_d.S
@@ -0,0 +1,49 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amominu_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amominu.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0xffffffff80000000, \
+ li a0, 0xffffffff80000000; \
+ li a1, 0xfffffffffffff800; \
+ la a3, amo_operand; \
+ sd a0, 0(a3); \
+ amominu.d a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3))
+
+ TEST_CASE(4, a4, 0, \
+ li a1, 0xffffffffffffffff; \
+ sd x0, 0(a3); \
+ amominu.d a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0, ld a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
+
diff --git a/tests/riscv-tests/rv32ua/amominu_w.S b/tests/riscv-tests/rv32ua/amominu_w.S
@@ -0,0 +1,62 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amominu_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amominu.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0xffffffff80000000, \
+ li a0, 0xffffffff80000000; \
+ li a1, 0xfffffffffffff800; \
+ la a3, amo_operand; \
+ sw a0, 0(a3); \
+ amominu.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3))
+
+ TEST_CASE(4, a4, 0, \
+ li a1, 0xffffffffffffffff; \
+ sw x0, 0(a3); \
+ amominu.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0, lw a5, 0(a3))
+
+ # The following two cases check that the upper 32 bits are ignored on rv64
+ # implementations. Only enable them for rv64.
+ #if __riscv_xlen == 64
+ TEST_CASE(6, a4, 1, \
+ li a0, 0x0000000000000001; \
+ li a1, 0x8000000000000000; \
+ la a3, amo_operand; \
+ sw a0, 0(a3); \
+ amominu.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(7, a5, 0, lw a5, 0(a3))
+ #endif
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
diff --git a/tests/riscv-tests/rv32ua/amoor_d.S b/tests/riscv-tests/rv32ua/amoor_d.S
@@ -0,0 +1,48 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoor_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amoor.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0xffffffff80000000, \
+ li a0, 0xffffffff80000000; \
+ li a1, 0xfffffffffffff800; \
+ la a3, amo_operand; \
+ sd a0, 0(a3); \
+ amoor.d a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3))
+
+ # try again after a cache miss
+ TEST_CASE(4, a4, 0xfffffffffffff800, \
+ li a1, 1; \
+ amoor.d a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0xfffffffffffff801, ld a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
diff --git a/tests/riscv-tests/rv32ua/amoor_w.S b/tests/riscv-tests/rv32ua/amoor_w.S
@@ -0,0 +1,48 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoor.w.S
+#-----------------------------------------------------------------------------
+#
+# Test amoor.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0xffffffff80000000, \
+ li a0, 0xffffffff80000000; \
+ li a1, 0xfffffffffffff800; \
+ la a3, amo_operand; \
+ sw a0, 0(a3); \
+ amoor.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3))
+
+ # try again after a cache miss
+ TEST_CASE(4, a4, 0xfffffffffffff800, \
+ li a1, 1; \
+ amoor.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0xfffffffffffff801, lw a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
diff --git a/tests/riscv-tests/rv32ua/amoswap_d.S b/tests/riscv-tests/rv32ua/amoswap_d.S
@@ -0,0 +1,48 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoswap.d.S
+#-----------------------------------------------------------------------------
+#
+# Test amoswap.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0xffffffff80000000, \
+ li a0, 0xffffffff80000000; \
+ li a1, 0xfffffffffffff800; \
+ la a3, amo_operand; \
+ sd a0, 0(a3); \
+ amoswap.d a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3))
+
+ # try again after a cache miss
+ TEST_CASE(4, a4, 0xfffffffffffff800, \
+ li a1, 0x0000000080000000; \
+ amoswap.d a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0x0000000080000000, ld a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
diff --git a/tests/riscv-tests/rv32ua/amoswap_w.S b/tests/riscv-tests/rv32ua/amoswap_w.S
@@ -0,0 +1,48 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoswap_w.S
+#-----------------------------------------------------------------------------
+#
+# Test amoswap.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0xffffffff80000000, \
+ li a0, 0xffffffff80000000; \
+ li a1, 0xfffffffffffff800; \
+ la a3, amo_operand; \
+ sw a0, 0(a3); \
+ amoswap.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3))
+
+ # try again after a cache miss
+ TEST_CASE(4, a4, 0xfffffffffffff800, \
+ li a1, 0x0000000080000000; \
+ amoswap.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0xffffffff80000000, lw a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
diff --git a/tests/riscv-tests/rv32ua/amoxor_d.S b/tests/riscv-tests/rv32ua/amoxor_d.S
@@ -0,0 +1,48 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoxor_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amoxor.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0xffffffff80000000, \
+ li a0, 0xffffffff80000000; \
+ li a1, 0xfffffffffffff800; \
+ la a3, amo_operand; \
+ sd a0, 0(a3); \
+ amoxor.d a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0x000000007ffff800, ld a5, 0(a3))
+
+ # try again after a cache miss
+ TEST_CASE(4, a4, 0x000000007ffff800, \
+ li a1, 1; \
+ amoxor.d a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0x000000007ffff801, ld a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
diff --git a/tests/riscv-tests/rv32ua/amoxor_w.S b/tests/riscv-tests/rv32ua/amoxor_w.S
@@ -0,0 +1,48 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoxor_w.S
+#-----------------------------------------------------------------------------
+#
+# Test amoxor.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0xffffffff80000000, \
+ li a0, 0xffffffff80000000; \
+ li a1, 0xfffffffffffff800; \
+ la a3, amo_operand; \
+ sw a0, 0(a3); \
+ amoxor.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0x7ffff800, lw a5, 0(a3))
+
+ # try again after a cache miss
+ TEST_CASE(4, a4, 0x7ffff800, \
+ li a1, 0xc0000001; \
+ amoxor.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0xffffffffbffff801, lw a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
diff --git a/tests/riscv-tests/rv32ua/lrsc.S b/tests/riscv-tests/rv32ua/lrsc.S
@@ -0,0 +1,111 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# lrsr.S
+#-----------------------------------------------------------------------------
+#
+# Test LR/SC instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+# get a unique core id
+la a0, coreid
+li a1, 1
+amoadd.w a2, a1, (a0)
+
+# for now, only run this on core 0
+1:li a3, 1
+bgeu a2, a3, 1b
+
+1: lw a1, (a0)
+bltu a1, a3, 1b
+
+# make sure that sc without a reservation fails.
+TEST_CASE( 2, a4, 1, \
+ la a0, foo; \
+ li a5, 0xdeadbeef; \
+ sc.w a4, a5, (a0); \
+)
+
+# make sure the failing sc did not commit into memory
+TEST_CASE( 3, a4, 0, \
+ lw a4, foo; \
+)
+
+#
+# Disable test case 4 for now. It assumes a <1K reservation granule, when
+# in reality any size granule is valid. After discussion in issue #315,
+# decided to simply disable the test for now.
+# (See https://github.com/riscv/riscv-tests/issues/315)
+#
+## make sure that sc with the wrong reservation fails.
+## TODO is this actually mandatory behavior?
+#TEST_CASE( 4, a4, 1, \
+# la a0, foo; \
+# la a1, fooTest3; \
+# lr.w a1, (a1); \
+# sc.w a4, a1, (a0); \
+#)
+
+#define LOG_ITERATIONS 10
+
+# have each core add its coreid+1 to foo 1024 times
+la a0, foo
+li a1, 1<<LOG_ITERATIONS
+addi a2, a2, 1
+1: lr.w a4, (a0)
+add a4, a4, a2
+sc.w a4, a4, (a0)
+bnez a4, 1b
+addi a1, a1, -1
+bnez a1, 1b
+
+# wait for all cores to finish
+la a0, barrier
+li a1, 1
+amoadd.w x0, a1, (a0)
+1: lw a1, (a0)
+blt a1, a3, 1b
+fence
+
+# expected result is 512*ncores*(ncores+1)
+TEST_CASE( 5, a0, 0, \
+ lw a0, foo; \
+ slli a1, a3, LOG_ITERATIONS-1; \
+1:sub a0, a0, a1; \
+ addi a3, a3, -1; \
+ bgez a3, 1b
+)
+
+# make sure that sc-after-successful-sc fails.
+TEST_CASE( 6, a1, 2, \
+ la a0, foo; \
+1:lr.w a1, (a0); \
+ sc.w a1, x0, (a0); \
+ bnez a1, 1b; \
+ sc.w a1, x0, (a0); \
+ /* make sure that sc-after-failed-sc fails, too */ \
+ sc.w a2, x0, (a0); \
+ add a1, a1, a2
+)
+
+TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+coreid: .word 0
+barrier: .word 0
+foo: .word 0
+.skip 1024
+fooTest3: .word 0
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ud/fadd.S b/tests/riscv-tests/rv32ud/fadd.S
@@ -0,0 +1,52 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fadd.S
+#-----------------------------------------------------------------------------
+#
+# Test f{add|sub|mul}.d instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+#if __riscv_xlen == 32
+ # Replace the function with the 32-bit variant defined in test_macros.h
+ #undef TEST_FP_OP2_D
+ #define TEST_FP_OP2_D TEST_FP_OP2_D32
+ #undef TEST_FP_OP2_D_HEX
+ #define TEST_FP_OP2_D_HEX TEST_FP_OP2_D32_HEX
+#endif
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_FP_OP2_D( 2, fadd.d, 0, 3.5, 2.5, 1.0 );
+ TEST_FP_OP2_D( 3, fadd.d, 1, -1234, -1235.1, 1.1 );
+ TEST_FP_OP2_D( 4, fadd.d, 1, 3.14159266, 3.14159265, 0.00000001 );
+
+ TEST_FP_OP2_D( 5, fsub.d, 0, 1.5, 2.5, 1.0 );
+ TEST_FP_OP2_D( 6, fsub.d, 1, -1234, -1235.1, -1.1 );
+ TEST_FP_OP2_D( 7, fsub.d, 1, 3.1415926400000001, 3.14159265, 0.00000001 );
+
+ TEST_FP_OP2_D( 8, fmul.d, 0, 2.5, 2.5, 1.0 );
+ TEST_FP_OP2_D( 9, fmul.d, 1, 1358.61, -1235.1, -1.1 );
+ TEST_FP_OP2_D(10, fmul.d, 1, 3.14159265e-8, 3.14159265, 0.00000001 );
+
+ # Is the canonical NaN generated for Inf - Inf?
+ TEST_FP_OP2_D_HEX(11, fsub.d, 0x10, qNaNd, Infd, Infd);
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ud/fclass.S b/tests/riscv-tests/rv32ud/fclass.S
@@ -0,0 +1,46 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fclass.S
+#-----------------------------------------------------------------------------
+#
+# Test fclass.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+#if __riscv_xlen == 32
+ # Replace the function with the 32-bit variant defined in test_macros.h
+ #undef TEST_FCLASS_D
+ #define TEST_FCLASS_D TEST_FCLASS_D32
+#endif
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_FCLASS_D( 2, 1 << 0, nInfd )
+ TEST_FCLASS_D( 3, 1 << 1, 0xbff0000000000000 )
+ TEST_FCLASS_D( 4, 1 << 2, 0x800fffffffffffff )
+ TEST_FCLASS_D( 5, 1 << 3, 0x8000000000000000 )
+ TEST_FCLASS_D( 6, 1 << 4, 0x0000000000000000 )
+ TEST_FCLASS_D( 7, 1 << 5, 0x000fffffffffffff )
+ TEST_FCLASS_D( 8, 1 << 6, 0x3ff0000000000000 )
+ TEST_FCLASS_D( 9, 1 << 7, Infd )
+ TEST_FCLASS_D(10, 1 << 8, sNaNd )
+ TEST_FCLASS_D(11, 1 << 9, qNaNd )
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ud/fcmp.S b/tests/riscv-tests/rv32ud/fcmp.S
@@ -0,0 +1,58 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fcmp.S
+#-----------------------------------------------------------------------------
+#
+# Test f{eq|lt|le}.d instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+#if __riscv_xlen == 32
+ # Replace the function with the 32-bit variant defined in test_macros.h
+ #undef TEST_FP_CMP_OP_D
+ #define TEST_FP_CMP_OP_D TEST_FP_CMP_OP_D32
+ #undef TEST_FP_CMP_OP_D_HEX
+ #define TEST_FP_CMP_OP_D_HEX TEST_FP_CMP_OP_D32_HEX
+#endif
+
+ TEST_FP_CMP_OP_D( 2, feq.d, 0x00, 1, -1.36, -1.36)
+ TEST_FP_CMP_OP_D( 3, fle.d, 0x00, 1, -1.36, -1.36)
+ TEST_FP_CMP_OP_D( 4, flt.d, 0x00, 0, -1.36, -1.36)
+
+ TEST_FP_CMP_OP_D( 5, feq.d, 0x00, 0, -1.37, -1.36)
+ TEST_FP_CMP_OP_D( 6, fle.d, 0x00, 1, -1.37, -1.36)
+ TEST_FP_CMP_OP_D( 7, flt.d, 0x00, 1, -1.37, -1.36)
+
+ # Only sNaN should signal invalid for feq.
+ TEST_FP_CMP_OP_D( 8, feq.d, 0x00, 0, NaN, 0)
+ TEST_FP_CMP_OP_D( 9, feq.d, 0x00, 0, NaN, NaN)
+ TEST_FP_CMP_OP_D_HEX(10, feq.d, 0x10, 0, sNaNd, 0)
+
+ # qNaN should signal invalid for fle/flt.
+ TEST_FP_CMP_OP_D(11, flt.d, 0x10, 0, NaN, 0)
+ TEST_FP_CMP_OP_D(12, flt.d, 0x10, 0, NaN, NaN)
+ TEST_FP_CMP_OP_D_HEX(13, flt.d, 0x10, 0, sNaNd, 0)
+ TEST_FP_CMP_OP_D(14, fle.d, 0x10, 0, NaN, 0)
+ TEST_FP_CMP_OP_D(15, fle.d, 0x10, 0, NaN, NaN)
+ TEST_FP_CMP_OP_D_HEX(16, fle.d, 0x10, 0, sNaNd, 0)
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ud/fcvt.S b/tests/riscv-tests/rv32ud/fcvt.S
@@ -0,0 +1,79 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fcvt.S
+#-----------------------------------------------------------------------------
+#
+# Test fcvt.d.{wu|w|lu|l}, fcvt.s.d, and fcvt.d.s instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+#if __riscv_xlen == 32
+ # Replace the function with the 32-bit variant defined in test_macros.h
+ #undef TEST_INT_FP_OP_D
+ #define TEST_INT_FP_OP_D TEST_INT_FP_OP_D32
+
+ #undef TEST_FCVT_S_D
+ #define TEST_FCVT_S_D TEST_FCVT_S_D32
+#endif
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_INT_FP_OP_D(2, fcvt.d.w, 2.0, 2);
+ TEST_INT_FP_OP_D(3, fcvt.d.w, -2.0, -2);
+
+ TEST_INT_FP_OP_D(4, fcvt.d.wu, 2.0, 2);
+ TEST_INT_FP_OP_D(5, fcvt.d.wu, 4294967294, -2);
+
+#if __riscv_xlen >= 64
+ TEST_INT_FP_OP_D(6, fcvt.d.l, 2.0, 2);
+ TEST_INT_FP_OP_D(7, fcvt.d.l, -2.0, -2);
+
+ TEST_INT_FP_OP_D(8, fcvt.d.lu, 2.0, 2);
+ TEST_INT_FP_OP_D(9, fcvt.d.lu, 1.8446744073709552e19, -2);
+#endif
+
+ TEST_FCVT_S_D(10, -1.5, -1.5)
+ TEST_FCVT_D_S(11, -1.5, -1.5)
+
+#if __riscv_xlen >= 64
+ TEST_CASE(12, a0, qNaNd,
+ la a1, test_data_22;
+ ld a2, 0(a1);
+ fmv.d.x f2, a2;
+ fcvt.s.d f2, f2;
+ fcvt.d.s f2, f2;
+ fmv.x.d a0, f2;
+ )
+#else
+ TEST_CASE_D32(12, a0, a1, qNaNd,
+ la a1, test_data_22;
+ fld f2, 0(a1);
+ fcvt.s.d f2, f2;
+ fcvt.d.s f2, f2;
+ fsd f2, 0(a1);
+ lw a0, 0(a1);
+ lw a1, 4(a1)
+ )
+#endif
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+test_data_22:
+ .dword 0x7ffcffffffff8004
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ud/fcvt_w.S b/tests/riscv-tests/rv32ud/fcvt_w.S
@@ -0,0 +1,114 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fcvt_w.S
+#-----------------------------------------------------------------------------
+#
+# Test fcvt{wu|w|lu|l}.d instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_FP_INT_OP_D( 2, fcvt.w.d, 0x01, -1, -1.1, rtz);
+ TEST_FP_INT_OP_D( 3, fcvt.w.d, 0x00, -1, -1.0, rtz);
+ TEST_FP_INT_OP_D( 4, fcvt.w.d, 0x01, 0, -0.9, rtz);
+ TEST_FP_INT_OP_D( 5, fcvt.w.d, 0x01, 0, 0.9, rtz);
+ TEST_FP_INT_OP_D( 6, fcvt.w.d, 0x00, 1, 1.0, rtz);
+ TEST_FP_INT_OP_D( 7, fcvt.w.d, 0x01, 1, 1.1, rtz);
+ TEST_FP_INT_OP_D( 8, fcvt.w.d, 0x10, -1<<31, -3e9, rtz);
+ TEST_FP_INT_OP_D( 9, fcvt.w.d, 0x10, (1<<31)-1, 3e9, rtz);
+
+ TEST_FP_INT_OP_D(12, fcvt.wu.d, 0x10, 0, -3.0, rtz);
+ TEST_FP_INT_OP_D(13, fcvt.wu.d, 0x10, 0, -1.0, rtz);
+ TEST_FP_INT_OP_D(14, fcvt.wu.d, 0x01, 0, -0.9, rtz);
+ TEST_FP_INT_OP_D(15, fcvt.wu.d, 0x01, 0, 0.9, rtz);
+ TEST_FP_INT_OP_D(16, fcvt.wu.d, 0x00, 1, 1.0, rtz);
+ TEST_FP_INT_OP_D(17, fcvt.wu.d, 0x01, 1, 1.1, rtz);
+ TEST_FP_INT_OP_D(18, fcvt.wu.d, 0x10, 0, -3e9, rtz);
+ TEST_FP_INT_OP_D(19, fcvt.wu.d, 0x00, 0xffffffffb2d05e00, 3e9, rtz);
+
+#if __riscv_xlen >= 64
+ TEST_FP_INT_OP_D(22, fcvt.l.d, 0x01, -1, -1.1, rtz);
+ TEST_FP_INT_OP_D(23, fcvt.l.d, 0x00, -1, -1.0, rtz);
+ TEST_FP_INT_OP_D(24, fcvt.l.d, 0x01, 0, -0.9, rtz);
+ TEST_FP_INT_OP_D(25, fcvt.l.d, 0x01, 0, 0.9, rtz);
+ TEST_FP_INT_OP_D(26, fcvt.l.d, 0x00, 1, 1.0, rtz);
+ TEST_FP_INT_OP_D(27, fcvt.l.d, 0x01, 1, 1.1, rtz);
+ TEST_FP_INT_OP_D(28, fcvt.l.d, 0x00,-3000000000, -3e9, rtz);
+ TEST_FP_INT_OP_D(29, fcvt.l.d, 0x00, 3000000000, 3e9, rtz);
+ TEST_FP_INT_OP_D(20, fcvt.l.d, 0x10, -1<<63,-3e19, rtz);
+ TEST_FP_INT_OP_D(21, fcvt.l.d, 0x10, (1<<63)-1, 3e19, rtz);
+
+ TEST_FP_INT_OP_D(32, fcvt.lu.d, 0x10, 0, -3.0, rtz);
+ TEST_FP_INT_OP_D(33, fcvt.lu.d, 0x10, 0, -1.0, rtz);
+ TEST_FP_INT_OP_D(34, fcvt.lu.d, 0x01, 0, -0.9, rtz);
+ TEST_FP_INT_OP_D(35, fcvt.lu.d, 0x01, 0, 0.9, rtz);
+ TEST_FP_INT_OP_D(36, fcvt.lu.d, 0x00, 1, 1.0, rtz);
+ TEST_FP_INT_OP_D(37, fcvt.lu.d, 0x01, 1, 1.1, rtz);
+ TEST_FP_INT_OP_D(38, fcvt.lu.d, 0x10, 0, -3e9, rtz);
+ TEST_FP_INT_OP_D(39, fcvt.lu.d, 0x00, 3000000000, 3e9, rtz);
+#endif
+
+ # test negative NaN, negative infinity conversion
+ TEST_CASE(42, x1, 0x000000007fffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.w.d x1, f1)
+#if __riscv_xlen >= 64
+ TEST_CASE(43, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.l.d x1, f1)
+#endif
+ TEST_CASE(44, x1, 0xffffffff80000000, la x1, tdat_d; fld f1, 16(x1); fcvt.w.d x1, f1)
+#if __riscv_xlen >= 64
+ TEST_CASE(45, x1, 0x8000000000000000, la x1, tdat_d; fld f1, 16(x1); fcvt.l.d x1, f1)
+#endif
+
+ # test positive NaN, positive infinity conversion
+ TEST_CASE(52, x1, 0x000000007fffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.w.d x1, f1)
+#if __riscv_xlen >= 64
+ TEST_CASE(53, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.l.d x1, f1)
+#endif
+ TEST_CASE(54, x1, 0x000000007fffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.w.d x1, f1)
+#if __riscv_xlen >= 64
+ TEST_CASE(55, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.l.d x1, f1)
+#endif
+
+ # test NaN, infinity conversions to unsigned integer
+ TEST_CASE(62, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.wu.d x1, f1)
+ TEST_CASE(63, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.wu.d x1, f1)
+ TEST_CASE(64, x1, 0, la x1, tdat_d; fld f1, 16(x1); fcvt.wu.d x1, f1)
+ TEST_CASE(65, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.wu.d x1, f1)
+#if __riscv_xlen >= 64
+ TEST_CASE(66, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.lu.d x1, f1)
+ TEST_CASE(67, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.lu.d x1, f1)
+ TEST_CASE(68, x1, 0, la x1, tdat_d; fld f1, 16(x1); fcvt.lu.d x1, f1)
+ TEST_CASE(69, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.lu.d x1, f1)
+#endif
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+# -NaN, NaN, -inf, +inf
+tdat:
+.word 0xffffffff
+.word 0x7fffffff
+.word nInff
+.word Inff
+
+tdat_d:
+.dword 0xffffffffffffffff
+.dword 0x7fffffffffffffff
+.dword nInfd
+.dword Infd
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ud/fdiv.S b/tests/riscv-tests/rv32ud/fdiv.S
@@ -0,0 +1,54 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fdiv.S
+#-----------------------------------------------------------------------------
+#
+# Test f{div|sqrt}.d instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+#if __riscv_xlen == 32
+ # Replace the functions with the 32-bit variants defined in test_macros.h
+ #undef TEST_FP_OP2_D
+ #define TEST_FP_OP2_D TEST_FP_OP2_D32
+
+ #undef TEST_FP_OP1_D
+ #define TEST_FP_OP1_D TEST_FP_OP1_D32
+
+ #undef TEST_FP_OP1_D_DWORD_RESULT
+ #define TEST_FP_OP1_D_DWORD_RESULT TEST_FP_OP1_D32_DWORD_RESULT
+#endif
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_FP_OP2_D( 2, fdiv.d, 1, 1.1557273520668288, 3.14159265, 2.71828182 );
+ TEST_FP_OP2_D( 3, fdiv.d, 1,-0.9991093838555584, -1234, 1235.1 );
+ TEST_FP_OP2_D( 4, fdiv.d, 0, 3.14159265, 3.14159265, 1.0 );
+
+ TEST_FP_OP1_D( 5, fsqrt.d, 1, 1.7724538498928541, 3.14159265 );
+ TEST_FP_OP1_D( 6, fsqrt.d, 0, 100, 10000 );
+
+ TEST_FP_OP1_D_DWORD_RESULT(16, fsqrt.d, 0x10, 0x7FF8000000000000, -1.0 );
+
+ TEST_FP_OP1_D( 7, fsqrt.d, 1, 13.076696830622021, 171.0);
+
+ TEST_FP_OP1_D( 8, fsqrt.d, 1,0.00040099251863345283320230749702, 1.60795e-7);
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ud/fmadd.S b/tests/riscv-tests/rv32ud/fmadd.S
@@ -0,0 +1,51 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fmadd.S
+#-----------------------------------------------------------------------------
+#
+# Test f[n]m{add|sub}.s and f[n]m{add|sub}.d instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+#if __riscv_xlen == 32
+ # Replace the function with the 32-bit variant defined in test_macros.h
+ #undef TEST_FP_OP3_D
+ #define TEST_FP_OP3_D TEST_FP_OP3_D32
+#endif
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_FP_OP3_D( 2, fmadd.d, 0, 3.5, 1.0, 2.5, 1.0 );
+ TEST_FP_OP3_D( 3, fmadd.d, 1, 1236.1999999999999, -1.0, -1235.1, 1.1 );
+ TEST_FP_OP3_D( 4, fmadd.d, 0, -12.0, 2.0, -5.0, -2.0 );
+
+ TEST_FP_OP3_D( 5, fnmadd.d, 0, -3.5, 1.0, 2.5, 1.0 );
+ TEST_FP_OP3_D( 6, fnmadd.d, 1, -1236.1999999999999, -1.0, -1235.1, 1.1 );
+ TEST_FP_OP3_D( 7, fnmadd.d, 0, 12.0, 2.0, -5.0, -2.0 );
+
+ TEST_FP_OP3_D( 8, fmsub.d, 0, 1.5, 1.0, 2.5, 1.0 );
+ TEST_FP_OP3_D( 9, fmsub.d, 1, 1234, -1.0, -1235.1, 1.1 );
+ TEST_FP_OP3_D(10, fmsub.d, 0, -8.0, 2.0, -5.0, -2.0 );
+
+ TEST_FP_OP3_D(11, fnmsub.d, 0, -1.5, 1.0, 2.5, 1.0 );
+ TEST_FP_OP3_D(12, fnmsub.d, 1, -1234, -1.0, -1235.1, 1.1 );
+ TEST_FP_OP3_D(13, fnmsub.d, 0, 8.0, 2.0, -5.0, -2.0 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ud/fmin.S b/tests/riscv-tests/rv32ud/fmin.S
@@ -0,0 +1,62 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fmin.S
+#-----------------------------------------------------------------------------
+#
+# Test f{min|max}.d instructinos.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+#if __riscv_xlen == 32
+ # Replace the function with the 32-bit variant defined in test_macros.h
+ #undef TEST_FP_OP2_D
+ #define TEST_FP_OP2_D TEST_FP_OP2_D32
+ #undef TEST_FP_OP2_D_HEX
+ #define TEST_FP_OP2_D_HEX TEST_FP_OP2_D32_HEX
+#endif
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_FP_OP2_D( 2, fmin.d, 0, 1.0, 2.5, 1.0 );
+ TEST_FP_OP2_D( 3, fmin.d, 0, -1235.1, -1235.1, 1.1 );
+ TEST_FP_OP2_D( 4, fmin.d, 0, -1235.1, 1.1, -1235.1 );
+ TEST_FP_OP2_D( 5, fmin.d, 0, -1235.1, NaN, -1235.1 );
+ TEST_FP_OP2_D( 6, fmin.d, 0, 0.00000001, 3.14159265, 0.00000001 );
+ TEST_FP_OP2_D( 7, fmin.d, 0, -2.0, -1.0, -2.0 );
+
+ TEST_FP_OP2_D(12, fmax.d, 0, 2.5, 2.5, 1.0 );
+ TEST_FP_OP2_D(13, fmax.d, 0, 1.1, -1235.1, 1.1 );
+ TEST_FP_OP2_D(14, fmax.d, 0, 1.1, 1.1, -1235.1 );
+ TEST_FP_OP2_D(15, fmax.d, 0, -1235.1, NaN, -1235.1 );
+ TEST_FP_OP2_D(16, fmax.d, 0, 3.14159265, 3.14159265, 0.00000001 );
+ TEST_FP_OP2_D(17, fmax.d, 0, -1.0, -1.0, -2.0 );
+
+ # FMAX(sNaN, x) = x
+ TEST_FP_OP2_D_HEX(20, fmax.d, 0x10, 0x3ff0000000000000, sNaNd, 0x3ff0000000000000);
+ # FMAX(qNaN, qNaN) = canonical NaN
+ TEST_FP_OP2_D_HEX(21, fmax.d, 0x00, qNaNd, 0x7fffffffffffffff, 0x7fffffffffffffff);
+
+ # -0.0 < +0.0
+ TEST_FP_OP2_D(30, fmin.d, 0, -0.0, -0.0, 0.0 );
+ TEST_FP_OP2_D(31, fmin.d, 0, -0.0, 0.0, -0.0 );
+ TEST_FP_OP2_D(32, fmax.d, 0, 0.0, -0.0, 0.0 );
+ TEST_FP_OP2_D(33, fmax.d, 0, 0.0, 0.0, -0.0 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ud/ldst.S b/tests/riscv-tests/rv32ud/ldst.S
@@ -0,0 +1,42 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# ldst.S
+#-----------------------------------------------------------------------------
+#
+# This test verifies that flw, fld, fsw, and fsd work properly.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32UF
+RVTEST_CODE_BEGIN
+
+ la s0, tdat
+ TEST_CASE_D32(2, a0, a1, 0x40000000bf800000, fld f2, 0(s0); fsd f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0))
+ TEST_CASE_D32(3, a0, a1, 0x40000000bf800000, fld f2, 0(s0); fsw f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0))
+ TEST_CASE_D32(4, a0, a1, 0x40000000bf800000, flw f2, 0(s0); fsw f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0))
+ TEST_CASE_D32(5, a0, a1, 0xc080000040400000, fld f2, 8(s0); fsd f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0))
+ TEST_CASE_D32(6, a0, a1, 0xffffffff40400000, flw f2, 8(s0); fsd f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+tdat:
+.word 0xbf800000
+.word 0x40000000
+.word 0x40400000
+.word 0xc0800000
+.word 0xdeadbeef
+.word 0xcafebabe
+.word 0xabad1dea
+.word 0x1337d00d
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ud/move.S b/tests/riscv-tests/rv32ud/move.S
@@ -0,0 +1,113 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# move.S
+#-----------------------------------------------------------------------------
+#
+# This test verifies that fmv.d.x, fmv.x.d, and fsgnj[x|n].d work properly.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+#TODO: make 32-bit compatible version
+#define TEST_FSGNJD(n, insn, new_sign, rs1_sign, rs2_sign) \
+ TEST_CASE(n, a0, 0x123456789abcdef0 | (-(new_sign) << 63), \
+ li a1, ((rs1_sign) << 63) | 0x123456789abcdef0; \
+ li a2, -(rs2_sign); \
+ fmv.d.x f1, a1; \
+ fmv.d.x f2, a2; \
+ insn f0, f1, f2; \
+ fmv.x.d a0, f0)
+
+ TEST_FSGNJD(10, fsgnj.d, 0, 0, 0)
+ TEST_FSGNJD(11, fsgnj.d, 1, 0, 1)
+ TEST_FSGNJD(12, fsgnj.d, 0, 1, 0)
+ TEST_FSGNJD(13, fsgnj.d, 1, 1, 1)
+
+ TEST_FSGNJD(20, fsgnjn.d, 1, 0, 0)
+ TEST_FSGNJD(21, fsgnjn.d, 0, 0, 1)
+ TEST_FSGNJD(22, fsgnjn.d, 1, 1, 0)
+ TEST_FSGNJD(23, fsgnjn.d, 0, 1, 1)
+
+ TEST_FSGNJD(30, fsgnjx.d, 0, 0, 0)
+ TEST_FSGNJD(31, fsgnjx.d, 1, 0, 1)
+ TEST_FSGNJD(32, fsgnjx.d, 1, 1, 0)
+ TEST_FSGNJD(33, fsgnjx.d, 0, 1, 1)
+
+// Test fsgnj.s in conjunction with double-precision moves
+#define TEST_FSGNJS(n, rd, rs1, rs2) \
+ TEST_CASE(n, a0, (rd) | (-((rd) >> 31) << 32), \
+ li a1, rs1; \
+ li a2, rs2; \
+ fmv.d.x f1, a1; \
+ fmv.d.x f2, a2; \
+ fsgnj.s f0, f1, f2; \
+ fmv.x.s a0, f0); \
+ TEST_CASE(1##n, a0, (rd) | 0xffffffff00000000, \
+ li a1, rs1; \
+ li a2, rs2; \
+ fmv.d.x f1, a1; \
+ fmv.d.x f2, a2; \
+ fsgnj.s f0, f1, f2; \
+ fmv.x.d a0, f0)
+
+ TEST_FSGNJS(40, qNaNf, 0x7ffffffe12345678, 0)
+ TEST_FSGNJS(41, qNaNf, 0xfffffffe12345678, 0)
+ TEST_FSGNJS(42, qNaNf, 0x7fffffff12345678, 0)
+ TEST_FSGNJS(43, 0x12345678, 0xffffffff12345678, 0)
+
+ TEST_FSGNJS(50, qNaNf, 0x7ffffffe12345678, 0x80000000)
+ TEST_FSGNJS(51, qNaNf, 0xfffffffe12345678, 0x80000000)
+ TEST_FSGNJS(52, qNaNf, 0x7fffffff12345678, 0x80000000)
+ TEST_FSGNJS(53, 0x12345678, 0xffffffff12345678, 0x80000000)
+
+ TEST_FSGNJS(60, 0xffc00000, 0x7ffffffe12345678, 0xffffffff80000000)
+ TEST_FSGNJS(61, 0xffc00000, 0xfffffffe12345678, 0xffffffff80000000)
+ TEST_FSGNJS(62, 0x92345678, 0xffffffff12345678, 0xffffffff80000000)
+ TEST_FSGNJS(63, 0x12345678, 0xffffffff12345678, 0x7fffffff80000000)
+
+// Test fsgnj.d in conjunction with single-precision moves
+#define TEST_FSGNJD_SP(n, isnan, rd, rs1, rs2) \
+ TEST_CASE(n, a0, ((rd) & 0xffffffff) | (-(((rd) >> 31) & 1) << 32), \
+ li a1, rs1; \
+ li a2, rs2; \
+ fmv.d.x f1, a1; \
+ fmv.d.x f2, a2; \
+ fsgnj.d f0, f1, f2; \
+ feq.s a0, f0, f0; \
+ addi a0, a0, -!(isnan); \
+ bnez a0, 1f; \
+ fmv.x.s a0, f0; \
+ 1:); \
+ TEST_CASE(1##n, a0, rd, \
+ li a1, rs1; \
+ li a2, rs2; \
+ fmv.d.x f1, a1; \
+ fmv.d.x f2, a2; \
+ fsgnj.d f0, f1, f2; \
+ fmv.x.d a0, f0; \
+ 1:)
+
+ TEST_FSGNJD_SP(70, 0, 0xffffffff11111111, 0xffffffff11111111, 0xffffffff11111111)
+ TEST_FSGNJD_SP(71, 1, 0x7fffffff11111111, 0xffffffff11111111, 0x7fffffff11111111)
+ TEST_FSGNJD_SP(72, 0, 0xffffffff11111111, 0xffffffff11111111, 0xffffffff91111111)
+ TEST_FSGNJD_SP(73, 0, 0xffffffff11111111, 0xffffffff11111111, 0x8000000000000000)
+ TEST_FSGNJD_SP(74, 0, 0xffffffff11111111, 0x7fffffff11111111, 0xffffffff11111111)
+ TEST_FSGNJD_SP(75, 1, 0x7fffffff11111111, 0x7fffffff11111111, 0x7fffffff11111111)
+ TEST_FSGNJD_SP(76, 0, 0xffffffff11111111, 0x7fffffff11111111, 0xffffffff91111111)
+ TEST_FSGNJD_SP(77, 0, 0xffffffff11111111, 0x7fffffff11111111, 0x8000000000000000)
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ud/recoding.S b/tests/riscv-tests/rv32ud/recoding.S
@@ -0,0 +1,67 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# recoding.S
+#-----------------------------------------------------------------------------
+#
+# Test corner cases of John Hauser's microarchitectural recoding scheme.
+# There are twice as many recoded values as IEEE-754 values; some of these
+# extras are redundant (e.g. Inf) and others are illegal (subnormals with
+# too many bits set).
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+ # Make sure infinities with different mantissas compare as equal.
+ fld f0, minf, a0
+ fld f1, three, a0
+ fmul.d f1, f1, f0
+ TEST_CASE( 2, a0, 1, feq.d a0, f0, f1)
+ TEST_CASE( 3, a0, 1, fle.d a0, f0, f1)
+ TEST_CASE( 4, a0, 0, flt.d a0, f0, f1)
+
+ # Likewise, but for zeroes.
+ fcvt.d.w f0, x0
+ li a0, 1
+ fcvt.d.w f1, a0
+ fmul.d f1, f1, f0
+ TEST_CASE(5, a0, 1, feq.d a0, f0, f1)
+ TEST_CASE(6, a0, 1, fle.d a0, f0, f1)
+ TEST_CASE(7, a0, 0, flt.d a0, f0, f1)
+
+ # When converting small doubles to single-precision subnormals,
+ # ensure that the extra precision is discarded.
+ flw f0, big, a0
+ fld f1, tiny, a0
+ fcvt.s.d f1, f1
+ fmul.s f0, f0, f1
+ fmv.x.s a0, f0
+ lw a1, small
+ TEST_CASE(10, a0, 0, sub a0, a0, a1)
+
+ # Make sure FSD+FLD correctly saves and restores a single-precision value.
+ flw f0, three, a0
+ fadd.s f1, f0, f0
+ fadd.s f0, f0, f0
+ fsd f0, tiny, a0
+ fld f0, tiny, a0
+ TEST_CASE(20, a0, 1, feq.s a0, f0, f1)
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+minf: .double -Inf
+three: .double 3.0
+big: .float 1221
+small: .float 2.9133121e-37
+tiny: .double 2.3860049081905093e-40
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ud/structural.S b/tests/riscv-tests/rv32ud/structural.S
@@ -0,0 +1,60 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# structural.S
+#-----------------------------------------------------------------------------
+#
+# This test verifies that the FPU correctly obviates structural hazards on its
+# writeback port (e.g. fadd followed by fsgnj)
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+li x12, 1
+
+li x2, 0x3FF0000000000000
+li x1, 0x3F800000
+
+#define TEST(testnum, nops) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ fmv.d.x f4, x0 ;\
+ fmv.s.x f3, x0 ;\
+ fmv.d.x f2, x2 ;\
+ fmv.s.x f1, x1 ;\
+ j 1f ;\
+ .align 5 ;\
+1:fmul.d f4, f2, f2 ;\
+ nops ;\
+ fsgnj.s f3, f1, f1 ;\
+ fmv.x.d x4, f4 ;\
+ fmv.x.s x5, f3 ;\
+ beq x1, x5, 2f ;\
+ j fail;\
+2:beq x2, x4, 2f ;\
+ j fail; \
+2:fmv.d.x f2, zero ;\
+ fmv.s.x f1, zero ;\
+
+TEST(1,;)
+TEST(2,nop)
+TEST(3,nop;nop)
+TEST(4,nop;nop;nop)
+TEST(5,nop;nop;nop;nop)
+TEST(6,nop;nop;nop;nop;nop)
+TEST(7,nop;nop;nop;nop;nop;nop)
+
+TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32uf/fadd.S b/tests/riscv-tests/rv32uf/fadd.S
@@ -0,0 +1,44 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fadd.S
+#-----------------------------------------------------------------------------
+#
+# Test f{add|sub|mul}.s instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_FP_OP2_S( 2, fadd.s, 0, 3.5, 2.5, 1.0 );
+ TEST_FP_OP2_S( 3, fadd.s, 1, -1234, -1235.1, 1.1 );
+ TEST_FP_OP2_S( 4, fadd.s, 1, 3.14159265, 3.14159265, 0.00000001 );
+
+ TEST_FP_OP2_S( 5, fsub.s, 0, 1.5, 2.5, 1.0 );
+ TEST_FP_OP2_S( 6, fsub.s, 1, -1234, -1235.1, -1.1 );
+ TEST_FP_OP2_S( 7, fsub.s, 1, 3.14159265, 3.14159265, 0.00000001 );
+
+ TEST_FP_OP2_S( 8, fmul.s, 0, 2.5, 2.5, 1.0 );
+ TEST_FP_OP2_S( 9, fmul.s, 1, 1358.61, -1235.1, -1.1 );
+ TEST_FP_OP2_S(10, fmul.s, 1, 3.14159265e-8, 3.14159265, 0.00000001 );
+
+ # Is the canonical NaN generated for Inf - Inf?
+ TEST_FP_OP2_S_HEX(11, fsub.s, 0x10, qNaNf, Inff, Inff);
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32uf/fclass.S b/tests/riscv-tests/rv32uf/fclass.S
@@ -0,0 +1,40 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fclass.S
+#-----------------------------------------------------------------------------
+#
+# Test fclass.s instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_FCLASS_S( 2, 1 << 0, nInff )
+ TEST_FCLASS_S( 3, 1 << 1, 0xbf800000 )
+ TEST_FCLASS_S( 4, 1 << 2, 0x807fffff )
+ TEST_FCLASS_S( 5, 1 << 3, 0x80000000 )
+ TEST_FCLASS_S( 6, 1 << 4, 0x00000000 )
+ TEST_FCLASS_S( 7, 1 << 5, 0x007fffff )
+ TEST_FCLASS_S( 8, 1 << 6, 0x3f800000 )
+ TEST_FCLASS_S( 9, 1 << 7, Inff )
+ TEST_FCLASS_S(10, 1 << 8, sNaNf )
+ TEST_FCLASS_S(11, 1 << 9, qNaNf )
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32uf/fcmp.S b/tests/riscv-tests/rv32uf/fcmp.S
@@ -0,0 +1,50 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fcmp.S
+#-----------------------------------------------------------------------------
+#
+# Test f{eq|lt|le}.s instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_FP_CMP_OP_S( 2, feq.s, 0x00, 1, -1.36, -1.36)
+ TEST_FP_CMP_OP_S( 3, fle.s, 0x00, 1, -1.36, -1.36)
+ TEST_FP_CMP_OP_S( 4, flt.s, 0x00, 0, -1.36, -1.36)
+
+ TEST_FP_CMP_OP_S( 5, feq.s, 0x00, 0, -1.37, -1.36)
+ TEST_FP_CMP_OP_S( 6, fle.s, 0x00, 1, -1.37, -1.36)
+ TEST_FP_CMP_OP_S( 7, flt.s, 0x00, 1, -1.37, -1.36)
+
+ # Only sNaN should signal invalid for feq.
+ TEST_FP_CMP_OP_S( 8, feq.s, 0x00, 0, NaN, 0)
+ TEST_FP_CMP_OP_S( 9, feq.s, 0x00, 0, NaN, NaN)
+ TEST_FP_CMP_OP_S_HEX(10, feq.s, 0x10, 0, sNaNf, 0)
+
+ # qNaN should signal invalid for fle/flt.
+ TEST_FP_CMP_OP_S(11, flt.s, 0x10, 0, NaN, 0)
+ TEST_FP_CMP_OP_S(12, flt.s, 0x10, 0, NaN, NaN)
+ TEST_FP_CMP_OP_S_HEX(13, flt.s, 0x10, 0, sNaNf, 0)
+ TEST_FP_CMP_OP_S(14, fle.s, 0x10, 0, NaN, 0)
+ TEST_FP_CMP_OP_S(15, fle.s, 0x10, 0, NaN, NaN)
+ TEST_FP_CMP_OP_S_HEX(16, fle.s, 0x10, 0, sNaNf, 0)
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32uf/fcvt.S b/tests/riscv-tests/rv32uf/fcvt.S
@@ -0,0 +1,43 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fcvt.S
+#-----------------------------------------------------------------------------
+#
+# Test fcvt.s.{wu|w|lu|l}, fcvt.s.d, and fcvt.d.s instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_INT_FP_OP_S( 2, fcvt.s.w, 2.0, 2);
+ TEST_INT_FP_OP_S( 3, fcvt.s.w, -2.0, -2);
+
+ TEST_INT_FP_OP_S( 4, fcvt.s.wu, 2.0, 2);
+ TEST_INT_FP_OP_S( 5, fcvt.s.wu, 4.2949673e9, -2);
+
+#if __riscv_xlen >= 64
+ TEST_INT_FP_OP_S( 6, fcvt.s.l, 2.0, 2);
+ TEST_INT_FP_OP_S( 7, fcvt.s.l, -2.0, -2);
+
+ TEST_INT_FP_OP_S( 8, fcvt.s.lu, 2.0, 2);
+ TEST_INT_FP_OP_S( 9, fcvt.s.lu, 1.8446744e19, -2);
+#endif
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32uf/fcvt_w.S b/tests/riscv-tests/rv32uf/fcvt_w.S
@@ -0,0 +1,105 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fcvt_w.S
+#-----------------------------------------------------------------------------
+#
+# Test fcvt{wu|w|lu|l}.s instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_FP_INT_OP_S( 2, fcvt.w.s, 0x01, -1, -1.1, rtz);
+ TEST_FP_INT_OP_S( 3, fcvt.w.s, 0x00, -1, -1.0, rtz);
+ TEST_FP_INT_OP_S( 4, fcvt.w.s, 0x01, 0, -0.9, rtz);
+ TEST_FP_INT_OP_S( 5, fcvt.w.s, 0x01, 0, 0.9, rtz);
+ TEST_FP_INT_OP_S( 6, fcvt.w.s, 0x00, 1, 1.0, rtz);
+ TEST_FP_INT_OP_S( 7, fcvt.w.s, 0x01, 1, 1.1, rtz);
+ TEST_FP_INT_OP_S( 8, fcvt.w.s, 0x10, -1<<31, -3e9, rtz);
+ TEST_FP_INT_OP_S( 9, fcvt.w.s, 0x10, (1<<31)-1, 3e9, rtz);
+
+ TEST_FP_INT_OP_S(12, fcvt.wu.s, 0x10, 0, -3.0, rtz);
+ TEST_FP_INT_OP_S(13, fcvt.wu.s, 0x10, 0, -1.0, rtz);
+ TEST_FP_INT_OP_S(14, fcvt.wu.s, 0x01, 0, -0.9, rtz);
+ TEST_FP_INT_OP_S(15, fcvt.wu.s, 0x01, 0, 0.9, rtz);
+ TEST_FP_INT_OP_S(16, fcvt.wu.s, 0x00, 1, 1.0, rtz);
+ TEST_FP_INT_OP_S(17, fcvt.wu.s, 0x01, 1, 1.1, rtz);
+ TEST_FP_INT_OP_S(18, fcvt.wu.s, 0x10, 0, -3e9, rtz);
+ TEST_FP_INT_OP_S(19, fcvt.wu.s, 0x00, 3000000000, 3e9, rtz);
+
+#if __riscv_xlen >= 64
+ TEST_FP_INT_OP_S(22, fcvt.l.s, 0x01, -1, -1.1, rtz);
+ TEST_FP_INT_OP_S(23, fcvt.l.s, 0x00, -1, -1.0, rtz);
+ TEST_FP_INT_OP_S(24, fcvt.l.s, 0x01, 0, -0.9, rtz);
+ TEST_FP_INT_OP_S(25, fcvt.l.s, 0x01, 0, 0.9, rtz);
+ TEST_FP_INT_OP_S(26, fcvt.l.s, 0x00, 1, 1.0, rtz);
+ TEST_FP_INT_OP_S(27, fcvt.l.s, 0x01, 1, 1.1, rtz);
+
+ TEST_FP_INT_OP_S(32, fcvt.lu.s, 0x10, 0, -3.0, rtz);
+ TEST_FP_INT_OP_S(33, fcvt.lu.s, 0x10, 0, -1.0, rtz);
+ TEST_FP_INT_OP_S(34, fcvt.lu.s, 0x01, 0, -0.9, rtz);
+ TEST_FP_INT_OP_S(35, fcvt.lu.s, 0x01, 0, 0.9, rtz);
+ TEST_FP_INT_OP_S(36, fcvt.lu.s, 0x00, 1, 1.0, rtz);
+ TEST_FP_INT_OP_S(37, fcvt.lu.s, 0x01, 1, 1.1, rtz);
+ TEST_FP_INT_OP_S(38, fcvt.lu.s, 0x10, 0, -3e9, rtz);
+#endif
+
+ # test negative NaN, negative infinity conversion
+ TEST_CASE( 42, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 0(x1); fcvt.w.s x1, f1)
+ TEST_CASE( 44, x1, 0xffffffff80000000, la x1, tdat ; flw f1, 8(x1); fcvt.w.s x1, f1)
+#if __riscv_xlen >= 64
+ TEST_CASE( 43, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 0(x1); fcvt.l.s x1, f1)
+ TEST_CASE( 45, x1, 0x8000000000000000, la x1, tdat ; flw f1, 8(x1); fcvt.l.s x1, f1)
+#endif
+
+ # test positive NaN, positive infinity conversion
+ TEST_CASE( 52, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 4(x1); fcvt.w.s x1, f1)
+ TEST_CASE( 54, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 12(x1); fcvt.w.s x1, f1)
+#if __riscv_xlen >= 64
+ TEST_CASE( 53, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.l.s x1, f1)
+ TEST_CASE( 55, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 12(x1); fcvt.l.s x1, f1)
+#endif
+
+ # test NaN, infinity conversions to unsigned integer
+ TEST_CASE( 62, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 0(x1); fcvt.wu.s x1, f1)
+ TEST_CASE( 63, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.wu.s x1, f1)
+ TEST_CASE( 64, x1, 0, la x1, tdat ; flw f1, 8(x1); fcvt.wu.s x1, f1)
+ TEST_CASE( 65, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 12(x1); fcvt.wu.s x1, f1)
+#if __riscv_xlen >= 64
+ TEST_CASE( 66, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 0(x1); fcvt.lu.s x1, f1)
+ TEST_CASE( 67, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.lu.s x1, f1)
+ TEST_CASE( 68, x1, 0, la x1, tdat ; flw f1, 8(x1); fcvt.lu.s x1, f1)
+ TEST_CASE( 69, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 12(x1); fcvt.lu.s x1, f1)
+#endif
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+# -NaN, NaN, -inf, +inf
+tdat:
+.word 0xffffffff
+.word 0x7fffffff
+.word nInff
+.word Inff
+
+tdat_d:
+.dword 0xffffffffffffffff
+.dword 0x7fffffffffffffff
+.dword nInfd
+.dword Infd
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32uf/fdiv.S b/tests/riscv-tests/rv32uf/fdiv.S
@@ -0,0 +1,40 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fdiv.S
+#-----------------------------------------------------------------------------
+#
+# Test f{div|sqrt}.s instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_FP_OP2_S(2, fdiv.s, 1, 1.1557273520668288, 3.14159265, 2.71828182 );
+ TEST_FP_OP2_S(3, fdiv.s, 1,-0.9991093838555584, -1234, 1235.1 );
+ TEST_FP_OP2_S(4, fdiv.s, 0, 3.14159265, 3.14159265, 1.0 );
+
+ TEST_FP_OP1_S(5, fsqrt.s, 1, 1.7724538498928541, 3.14159265 );
+ TEST_FP_OP1_S(6, fsqrt.s, 0, 100, 10000 );
+
+ TEST_FP_OP1_S_DWORD_RESULT(7, fsqrt.s, 0x10, 0x7FC00000, -1.0 );
+
+ TEST_FP_OP1_S(8, fsqrt.s, 1, 13.076696, 171.0);
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32uf/fmadd.S b/tests/riscv-tests/rv32uf/fmadd.S
@@ -0,0 +1,45 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fmadd.S
+#-----------------------------------------------------------------------------
+#
+# Test f[n]m{add|sub}.s and f[n]m{add|sub}.d instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_FP_OP3_S( 2, fmadd.s, 0, 3.5, 1.0, 2.5, 1.0 );
+ TEST_FP_OP3_S( 3, fmadd.s, 1, 1236.2, -1.0, -1235.1, 1.1 );
+ TEST_FP_OP3_S( 4, fmadd.s, 0, -12.0, 2.0, -5.0, -2.0 );
+
+ TEST_FP_OP3_S( 5, fnmadd.s, 0, -3.5, 1.0, 2.5, 1.0 );
+ TEST_FP_OP3_S( 6, fnmadd.s, 1, -1236.2, -1.0, -1235.1, 1.1 );
+ TEST_FP_OP3_S( 7, fnmadd.s, 0, 12.0, 2.0, -5.0, -2.0 );
+
+ TEST_FP_OP3_S( 8, fmsub.s, 0, 1.5, 1.0, 2.5, 1.0 );
+ TEST_FP_OP3_S( 9, fmsub.s, 1, 1234, -1.0, -1235.1, 1.1 );
+ TEST_FP_OP3_S(10, fmsub.s, 0, -8.0, 2.0, -5.0, -2.0 );
+
+ TEST_FP_OP3_S(11, fnmsub.s, 0, -1.5, 1.0, 2.5, 1.0 );
+ TEST_FP_OP3_S(12, fnmsub.s, 1, -1234, -1.0, -1235.1, 1.1 );
+ TEST_FP_OP3_S(13, fnmsub.s, 0, 8.0, 2.0, -5.0, -2.0 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32uf/fmin.S b/tests/riscv-tests/rv32uf/fmin.S
@@ -0,0 +1,54 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fmin.S
+#-----------------------------------------------------------------------------
+#
+# Test f{min|max}.s instructinos.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_FP_OP2_S( 2, fmin.s, 0, 1.0, 2.5, 1.0 );
+ TEST_FP_OP2_S( 3, fmin.s, 0, -1235.1, -1235.1, 1.1 );
+ TEST_FP_OP2_S( 4, fmin.s, 0, -1235.1, 1.1, -1235.1 );
+ TEST_FP_OP2_S( 5, fmin.s, 0, -1235.1, NaN, -1235.1 );
+ TEST_FP_OP2_S( 6, fmin.s, 0, 0.00000001, 3.14159265, 0.00000001 );
+ TEST_FP_OP2_S( 7, fmin.s, 0, -2.0, -1.0, -2.0 );
+
+ TEST_FP_OP2_S(12, fmax.s, 0, 2.5, 2.5, 1.0 );
+ TEST_FP_OP2_S(13, fmax.s, 0, 1.1, -1235.1, 1.1 );
+ TEST_FP_OP2_S(14, fmax.s, 0, 1.1, 1.1, -1235.1 );
+ TEST_FP_OP2_S(15, fmax.s, 0, -1235.1, NaN, -1235.1 );
+ TEST_FP_OP2_S(16, fmax.s, 0, 3.14159265, 3.14159265, 0.00000001 );
+ TEST_FP_OP2_S(17, fmax.s, 0, -1.0, -1.0, -2.0 );
+
+ # FMAX(sNaN, x) = x
+ TEST_FP_OP2_S_HEX(20, fmax.s, 0x10, 0x3f800000, sNaNf, 0x3f800000);
+ # FMAX(qNaN, qNaN) = canonical NaN
+ TEST_FP_OP2_S_HEX(21, fmax.s, 0x00, qNaNf, 0x7fffffff, 0x7fffffff);
+
+ # -0.0 < +0.0
+ TEST_FP_OP2_S(30, fmin.s, 0, -0.0, -0.0, 0.0 );
+ TEST_FP_OP2_S(31, fmin.s, 0, -0.0, 0.0, -0.0 );
+ TEST_FP_OP2_S(32, fmax.s, 0, 0.0, -0.0, 0.0 );
+ TEST_FP_OP2_S(33, fmax.s, 0, 0.0, 0.0, -0.0 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32uf/ldst.S b/tests/riscv-tests/rv32uf/ldst.S
@@ -0,0 +1,38 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# ldst.S
+#-----------------------------------------------------------------------------
+#
+# This test verifies that flw, fld, fsw, and fsd work properly.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32UF
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a0, 0x40000000, la a1, tdat; flw f1, 4(a1); fsw f1, 20(a1); lw a0, 20(a1))
+ TEST_CASE(3, a0, 0xbf800000, la a1, tdat; flw f1, 0(a1); fsw f1, 24(a1); lw a0, 24(a1))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+tdat:
+.word 0xbf800000
+.word 0x40000000
+.word 0x40400000
+.word 0xc0800000
+.word 0xdeadbeef
+.word 0xcafebabe
+.word 0xabad1dea
+.word 0x1337d00d
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32uf/move.S b/tests/riscv-tests/rv32uf/move.S
@@ -0,0 +1,58 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# move.S
+#-----------------------------------------------------------------------------
+#
+# This test verifies that the fmv.s.x, fmv.x.s, and fsgnj[x|n].d instructions
+# and the fcsr work properly.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a1, 1, csrwi fcsr, 1; li a0, 0x1234; fssr a1, a0)
+ TEST_CASE(3, a0, 0x34, frsr a0)
+ TEST_CASE(4, a0, 0x14, frflags a0)
+ TEST_CASE(5, a0, 0x01, csrrwi a0, frm, 2)
+ TEST_CASE(6, a0, 0x54, frsr a0)
+ TEST_CASE(7, a0, 0x14, csrrci a0, fflags, 4)
+ TEST_CASE(8, a0, 0x50, frsr a0)
+
+#define TEST_FSGNJS(n, insn, new_sign, rs1_sign, rs2_sign) \
+ TEST_CASE(n, a0, 0x12345678 | (-(new_sign) << 31), \
+ li a1, ((rs1_sign) << 31) | 0x12345678; \
+ li a2, -(rs2_sign); \
+ fmv.s.x f1, a1; \
+ fmv.s.x f2, a2; \
+ insn f0, f1, f2; \
+ fmv.x.s a0, f0)
+
+ TEST_FSGNJS(10, fsgnj.s, 0, 0, 0)
+ TEST_FSGNJS(11, fsgnj.s, 1, 0, 1)
+ TEST_FSGNJS(12, fsgnj.s, 0, 1, 0)
+ TEST_FSGNJS(13, fsgnj.s, 1, 1, 1)
+
+ TEST_FSGNJS(20, fsgnjn.s, 1, 0, 0)
+ TEST_FSGNJS(21, fsgnjn.s, 0, 0, 1)
+ TEST_FSGNJS(22, fsgnjn.s, 1, 1, 0)
+ TEST_FSGNJS(23, fsgnjn.s, 0, 1, 1)
+
+ TEST_FSGNJS(30, fsgnjx.s, 0, 0, 0)
+ TEST_FSGNJS(31, fsgnjx.s, 1, 0, 1)
+ TEST_FSGNJS(32, fsgnjx.s, 1, 1, 0)
+ TEST_FSGNJS(33, fsgnjx.s, 0, 1, 1)
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32uf/recoding.S b/tests/riscv-tests/rv32uf/recoding.S
@@ -0,0 +1,46 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# recoding.S
+#-----------------------------------------------------------------------------
+#
+# Test corner cases of John Hauser's microarchitectural recoding scheme.
+# There are twice as many recoded values as IEEE-754 values; some of these
+# extras are redundant (e.g. Inf) and others are illegal (subnormals with
+# too many bits set).
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+ # Make sure infinities with different mantissas compare as equal.
+ flw f0, minf, a0
+ flw f1, three, a0
+ fmul.s f1, f1, f0
+ TEST_CASE( 2, a0, 1, feq.s a0, f0, f1)
+ TEST_CASE( 3, a0, 1, fle.s a0, f0, f1)
+ TEST_CASE( 4, a0, 0, flt.s a0, f0, f1)
+
+ # Likewise, but for zeroes.
+ fcvt.s.w f0, x0
+ li a0, 1
+ fcvt.s.w f1, a0
+ fmul.s f1, f1, f0
+ TEST_CASE(5, a0, 1, feq.s a0, f0, f1)
+ TEST_CASE(6, a0, 1, fle.s a0, f0, f1)
+ TEST_CASE(7, a0, 0, flt.s a0, f0, f1)
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+minf: .float -Inf
+three: .float 3.0
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/add.S b/tests/riscv-tests/rv32ui/add.S
@@ -0,0 +1,85 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# add.S
+#-----------------------------------------------------------------------------
+#
+# Test add instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, add, 0x00000000, 0x00000000, 0x00000000 );
+ TEST_RR_OP( 3, add, 0x00000002, 0x00000001, 0x00000001 );
+ TEST_RR_OP( 4, add, 0x0000000a, 0x00000003, 0x00000007 );
+
+ TEST_RR_OP( 5, add, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 );
+ TEST_RR_OP( 6, add, 0xffffffff80000000, 0xffffffff80000000, 0x00000000 );
+ TEST_RR_OP( 7, add, 0xffffffff7fff8000, 0xffffffff80000000, 0xffffffffffff8000 );
+
+ TEST_RR_OP( 8, add, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff );
+ TEST_RR_OP( 9, add, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 );
+ TEST_RR_OP( 10, add, 0x0000000080007ffe, 0x000000007fffffff, 0x0000000000007fff );
+
+ TEST_RR_OP( 11, add, 0xffffffff80007fff, 0xffffffff80000000, 0x0000000000007fff );
+ TEST_RR_OP( 12, add, 0x000000007fff7fff, 0x000000007fffffff, 0xffffffffffff8000 );
+
+ TEST_RR_OP( 13, add, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff );
+ TEST_RR_OP( 14, add, 0x0000000000000000, 0xffffffffffffffff, 0x0000000000000001 );
+ TEST_RR_OP( 15, add, 0xfffffffffffffffe, 0xffffffffffffffff, 0xffffffffffffffff );
+
+ TEST_RR_OP( 16, add, 0x0000000080000000, 0x0000000000000001, 0x000000007fffffff );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 17, add, 24, 13, 11 );
+ TEST_RR_SRC2_EQ_DEST( 18, add, 25, 14, 11 );
+ TEST_RR_SRC12_EQ_DEST( 19, add, 26, 13 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 20, 0, add, 24, 13, 11 );
+ TEST_RR_DEST_BYPASS( 21, 1, add, 25, 14, 11 );
+ TEST_RR_DEST_BYPASS( 22, 2, add, 26, 15, 11 );
+
+ TEST_RR_SRC12_BYPASS( 23, 0, 0, add, 24, 13, 11 );
+ TEST_RR_SRC12_BYPASS( 24, 0, 1, add, 25, 14, 11 );
+ TEST_RR_SRC12_BYPASS( 25, 0, 2, add, 26, 15, 11 );
+ TEST_RR_SRC12_BYPASS( 26, 1, 0, add, 24, 13, 11 );
+ TEST_RR_SRC12_BYPASS( 27, 1, 1, add, 25, 14, 11 );
+ TEST_RR_SRC12_BYPASS( 28, 2, 0, add, 26, 15, 11 );
+
+ TEST_RR_SRC21_BYPASS( 29, 0, 0, add, 24, 13, 11 );
+ TEST_RR_SRC21_BYPASS( 30, 0, 1, add, 25, 14, 11 );
+ TEST_RR_SRC21_BYPASS( 31, 0, 2, add, 26, 15, 11 );
+ TEST_RR_SRC21_BYPASS( 32, 1, 0, add, 24, 13, 11 );
+ TEST_RR_SRC21_BYPASS( 33, 1, 1, add, 25, 14, 11 );
+ TEST_RR_SRC21_BYPASS( 34, 2, 0, add, 26, 15, 11 );
+
+ TEST_RR_ZEROSRC1( 35, add, 15, 15 );
+ TEST_RR_ZEROSRC2( 36, add, 32, 32 );
+ TEST_RR_ZEROSRC12( 37, add, 0 );
+ TEST_RR_ZERODEST( 38, add, 16, 30 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/addi.S b/tests/riscv-tests/rv32ui/addi.S
@@ -0,0 +1,71 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# addi.S
+#-----------------------------------------------------------------------------
+#
+# Test addi instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_OP( 2, addi, 0x00000000, 0x00000000, 0x000 );
+ TEST_IMM_OP( 3, addi, 0x00000002, 0x00000001, 0x001 );
+ TEST_IMM_OP( 4, addi, 0x0000000a, 0x00000003, 0x007 );
+
+ TEST_IMM_OP( 5, addi, 0xfffffffffffff800, 0x0000000000000000, 0x800 );
+ TEST_IMM_OP( 6, addi, 0xffffffff80000000, 0xffffffff80000000, 0x000 );
+ TEST_IMM_OP( 7, addi, 0xffffffff7ffff800, 0xffffffff80000000, 0x800 );
+
+ TEST_IMM_OP( 8, addi, 0x00000000000007ff, 0x00000000, 0x7ff );
+ TEST_IMM_OP( 9, addi, 0x000000007fffffff, 0x7fffffff, 0x000 );
+ TEST_IMM_OP( 10, addi, 0x00000000800007fe, 0x7fffffff, 0x7ff );
+
+ TEST_IMM_OP( 11, addi, 0xffffffff800007ff, 0xffffffff80000000, 0x7ff );
+ TEST_IMM_OP( 12, addi, 0x000000007ffff7ff, 0x000000007fffffff, 0x800 );
+
+ TEST_IMM_OP( 13, addi, 0xffffffffffffffff, 0x0000000000000000, 0xfff );
+ TEST_IMM_OP( 14, addi, 0x0000000000000000, 0xffffffffffffffff, 0x001 );
+ TEST_IMM_OP( 15, addi, 0xfffffffffffffffe, 0xffffffffffffffff, 0xfff );
+
+ TEST_IMM_OP( 16, addi, 0x0000000080000000, 0x7fffffff, 0x001 );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_SRC1_EQ_DEST( 17, addi, 24, 13, 11 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_DEST_BYPASS( 18, 0, addi, 24, 13, 11 );
+ TEST_IMM_DEST_BYPASS( 19, 1, addi, 23, 13, 10 );
+ TEST_IMM_DEST_BYPASS( 20, 2, addi, 22, 13, 9 );
+
+ TEST_IMM_SRC1_BYPASS( 21, 0, addi, 24, 13, 11 );
+ TEST_IMM_SRC1_BYPASS( 22, 1, addi, 23, 13, 10 );
+ TEST_IMM_SRC1_BYPASS( 23, 2, addi, 22, 13, 9 );
+
+ TEST_IMM_ZEROSRC1( 24, addi, 32, 32 );
+ TEST_IMM_ZERODEST( 25, addi, 33, 50 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/addiw.S b/tests/riscv-tests/rv32ui/addiw.S
@@ -0,0 +1,71 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# addiw.S
+#-----------------------------------------------------------------------------
+#
+# Test addiw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_OP( 2, addiw, 0x00000000, 0x00000000, 0x000 );
+ TEST_IMM_OP( 3, addiw, 0x00000002, 0x00000001, 0x001 );
+ TEST_IMM_OP( 4, addiw, 0x0000000a, 0x00000003, 0x007 );
+
+ TEST_IMM_OP( 5, addiw, 0xfffffffffffff800, 0x0000000000000000, 0x800 );
+ TEST_IMM_OP( 6, addiw, 0xffffffff80000000, 0xffffffff80000000, 0x000 );
+ TEST_IMM_OP( 7, addiw, 0x000000007ffff800, 0xffffffff80000000, 0x800 );
+
+ TEST_IMM_OP( 8, addiw, 0x00000000000007ff, 0x00000000, 0x7ff );
+ TEST_IMM_OP( 9, addiw, 0x000000007fffffff, 0x7fffffff, 0x000 );
+ TEST_IMM_OP( 10, addiw, 0xffffffff800007fe, 0x7fffffff, 0x7ff );
+
+ TEST_IMM_OP( 11, addiw, 0xffffffff800007ff, 0xffffffff80000000, 0x7ff );
+ TEST_IMM_OP( 12, addiw, 0x000000007ffff7ff, 0x000000007fffffff, 0x800 );
+
+ TEST_IMM_OP( 13, addiw, 0xffffffffffffffff, 0x0000000000000000, 0xfff );
+ TEST_IMM_OP( 14, addiw, 0x0000000000000000, 0xffffffffffffffff, 0x001 );
+ TEST_IMM_OP( 15, addiw, 0xfffffffffffffffe, 0xffffffffffffffff, 0xfff );
+
+ TEST_IMM_OP( 16, addiw, 0xffffffff80000000, 0x7fffffff, 0x001 );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_SRC1_EQ_DEST( 17, addiw, 24, 13, 11 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_DEST_BYPASS( 18, 0, addiw, 24, 13, 11 );
+ TEST_IMM_DEST_BYPASS( 19, 1, addiw, 23, 13, 10 );
+ TEST_IMM_DEST_BYPASS( 20, 2, addiw, 22, 13, 9 );
+
+ TEST_IMM_SRC1_BYPASS( 21, 0, addiw, 24, 13, 11 );
+ TEST_IMM_SRC1_BYPASS( 22, 1, addiw, 23, 13, 10 );
+ TEST_IMM_SRC1_BYPASS( 23, 2, addiw, 22, 13, 9 );
+
+ TEST_IMM_ZEROSRC1( 24, addiw, 32, 32 );
+ TEST_IMM_ZERODEST( 25, addiw, 33, 50 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/addw.S b/tests/riscv-tests/rv32ui/addw.S
@@ -0,0 +1,85 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# addw.S
+#-----------------------------------------------------------------------------
+#
+# Test addw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, addw, 0x00000000, 0x00000000, 0x00000000 );
+ TEST_RR_OP( 3, addw, 0x00000002, 0x00000001, 0x00000001 );
+ TEST_RR_OP( 4, addw, 0x0000000a, 0x00000003, 0x00000007 );
+
+ TEST_RR_OP( 5, addw, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 );
+ TEST_RR_OP( 6, addw, 0xffffffff80000000, 0xffffffff80000000, 0x00000000 );
+ TEST_RR_OP( 7, addw, 0x000000007fff8000, 0xffffffff80000000, 0xffffffffffff8000 );
+
+ TEST_RR_OP( 8, addw, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff );
+ TEST_RR_OP( 9, addw, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 );
+ TEST_RR_OP( 10, addw, 0xffffffff80007ffe, 0x000000007fffffff, 0x0000000000007fff );
+
+ TEST_RR_OP( 11, addw, 0xffffffff80007fff, 0xffffffff80000000, 0x0000000000007fff );
+ TEST_RR_OP( 12, addw, 0x000000007fff7fff, 0x000000007fffffff, 0xffffffffffff8000 );
+
+ TEST_RR_OP( 13, addw, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff );
+ TEST_RR_OP( 14, addw, 0x0000000000000000, 0xffffffffffffffff, 0x0000000000000001 );
+ TEST_RR_OP( 15, addw, 0xfffffffffffffffe, 0xffffffffffffffff, 0xffffffffffffffff );
+
+ TEST_RR_OP( 16, addw, 0xffffffff80000000, 0x0000000000000001, 0x000000007fffffff );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 17, addw, 24, 13, 11 );
+ TEST_RR_SRC2_EQ_DEST( 18, addw, 25, 14, 11 );
+ TEST_RR_SRC12_EQ_DEST( 19, addw, 26, 13 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 20, 0, addw, 24, 13, 11 );
+ TEST_RR_DEST_BYPASS( 21, 1, addw, 25, 14, 11 );
+ TEST_RR_DEST_BYPASS( 22, 2, addw, 26, 15, 11 );
+
+ TEST_RR_SRC12_BYPASS( 23, 0, 0, addw, 24, 13, 11 );
+ TEST_RR_SRC12_BYPASS( 24, 0, 1, addw, 25, 14, 11 );
+ TEST_RR_SRC12_BYPASS( 25, 0, 2, addw, 26, 15, 11 );
+ TEST_RR_SRC12_BYPASS( 26, 1, 0, addw, 24, 13, 11 );
+ TEST_RR_SRC12_BYPASS( 27, 1, 1, addw, 25, 14, 11 );
+ TEST_RR_SRC12_BYPASS( 28, 2, 0, addw, 26, 15, 11 );
+
+ TEST_RR_SRC21_BYPASS( 29, 0, 0, addw, 24, 13, 11 );
+ TEST_RR_SRC21_BYPASS( 30, 0, 1, addw, 25, 14, 11 );
+ TEST_RR_SRC21_BYPASS( 31, 0, 2, addw, 26, 15, 11 );
+ TEST_RR_SRC21_BYPASS( 32, 1, 0, addw, 24, 13, 11 );
+ TEST_RR_SRC21_BYPASS( 33, 1, 1, addw, 25, 14, 11 );
+ TEST_RR_SRC21_BYPASS( 34, 2, 0, addw, 26, 15, 11 );
+
+ TEST_RR_ZEROSRC1( 35, addw, 15, 15 );
+ TEST_RR_ZEROSRC2( 36, addw, 32, 32 );
+ TEST_RR_ZEROSRC12( 37, addw, 0 );
+ TEST_RR_ZERODEST( 38, addw, 16, 30 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/and.S b/tests/riscv-tests/rv32ui/and.S
@@ -0,0 +1,69 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# and.S
+#-----------------------------------------------------------------------------
+#
+# Test and instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Logical tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_OP( 3, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
+ TEST_RR_OP( 4, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
+ TEST_RR_OP( 5, and, 0xf000f000, 0xf00ff00f, 0xf0f0f0f0 );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 6, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_SRC2_EQ_DEST( 7, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
+ TEST_RR_SRC12_EQ_DEST( 8, and, 0xff00ff00, 0xff00ff00 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 9, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_DEST_BYPASS( 10, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
+ TEST_RR_DEST_BYPASS( 11, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
+
+ TEST_RR_SRC12_BYPASS( 12, 0, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_SRC12_BYPASS( 13, 0, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
+ TEST_RR_SRC12_BYPASS( 14, 0, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
+ TEST_RR_SRC12_BYPASS( 15, 1, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_SRC12_BYPASS( 16, 1, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
+ TEST_RR_SRC12_BYPASS( 17, 2, 0, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
+
+ TEST_RR_SRC21_BYPASS( 18, 0, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_SRC21_BYPASS( 19, 0, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
+ TEST_RR_SRC21_BYPASS( 20, 0, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
+ TEST_RR_SRC21_BYPASS( 21, 1, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_SRC21_BYPASS( 22, 1, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
+ TEST_RR_SRC21_BYPASS( 23, 2, 0, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
+
+ TEST_RR_ZEROSRC1( 24, and, 0, 0xff00ff00 );
+ TEST_RR_ZEROSRC2( 25, and, 0, 0x00ff00ff );
+ TEST_RR_ZEROSRC12( 26, and, 0 );
+ TEST_RR_ZERODEST( 27, and, 0x11111111, 0x22222222 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/andi.S b/tests/riscv-tests/rv32ui/andi.S
@@ -0,0 +1,55 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# andi.S
+#-----------------------------------------------------------------------------
+#
+# Test andi instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Logical tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_OP( 2, andi, 0xff00ff00, 0xff00ff00, 0xf0f );
+ TEST_IMM_OP( 3, andi, 0x000000f0, 0x0ff00ff0, 0x0f0 );
+ TEST_IMM_OP( 4, andi, 0x0000000f, 0x00ff00ff, 0x70f );
+ TEST_IMM_OP( 5, andi, 0x00000000, 0xf00ff00f, 0x0f0 );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_SRC1_EQ_DEST( 6, andi, 0x00000000, 0xff00ff00, 0x0f0 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_DEST_BYPASS( 7, 0, andi, 0x00000700, 0x0ff00ff0, 0x70f );
+ TEST_IMM_DEST_BYPASS( 8, 1, andi, 0x000000f0, 0x00ff00ff, 0x0f0 );
+ TEST_IMM_DEST_BYPASS( 9, 2, andi, 0xf00ff00f, 0xf00ff00f, 0xf0f );
+
+ TEST_IMM_SRC1_BYPASS( 10, 0, andi, 0x00000700, 0x0ff00ff0, 0x70f );
+ TEST_IMM_SRC1_BYPASS( 11, 1, andi, 0x000000f0, 0x00ff00ff, 0x0f0 );
+ TEST_IMM_SRC1_BYPASS( 12, 2, andi, 0x0000000f, 0xf00ff00f, 0x70f );
+
+ TEST_IMM_ZEROSRC1( 13, andi, 0, 0x0f0 );
+ TEST_IMM_ZERODEST( 14, andi, 0x00ff00ff, 0x70f );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/auipc.S b/tests/riscv-tests/rv32ui/auipc.S
@@ -0,0 +1,39 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# auipc.S
+#-----------------------------------------------------------------------------
+#
+# Test auipc instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a0, 10000, \
+ .align 3; \
+ lla a0, 1f + 10000; \
+ jal a1, 1f; \
+ 1: sub a0, a0, a1; \
+ )
+
+ TEST_CASE(3, a0, -10000, \
+ .align 3; \
+ lla a0, 1f - 10000; \
+ jal a1, 1f; \
+ 1: sub a0, a0, a1; \
+ )
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/beq.S b/tests/riscv-tests/rv32ui/beq.S
@@ -0,0 +1,73 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# beq.S
+#-----------------------------------------------------------------------------
+#
+# Test beq instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Branch tests
+ #-------------------------------------------------------------
+
+ # Each test checks both forward and backward branches
+
+ TEST_BR2_OP_TAKEN( 2, beq, 0, 0 );
+ TEST_BR2_OP_TAKEN( 3, beq, 1, 1 );
+ TEST_BR2_OP_TAKEN( 4, beq, -1, -1 );
+
+ TEST_BR2_OP_NOTTAKEN( 5, beq, 0, 1 );
+ TEST_BR2_OP_NOTTAKEN( 6, beq, 1, 0 );
+ TEST_BR2_OP_NOTTAKEN( 7, beq, -1, 1 );
+ TEST_BR2_OP_NOTTAKEN( 8, beq, 1, -1 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_BR2_SRC12_BYPASS( 9, 0, 0, beq, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 10, 0, 1, beq, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 11, 0, 2, beq, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 12, 1, 0, beq, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 13, 1, 1, beq, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 14, 2, 0, beq, 0, -1 );
+
+ TEST_BR2_SRC12_BYPASS( 15, 0, 0, beq, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 16, 0, 1, beq, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 17, 0, 2, beq, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 18, 1, 0, beq, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 19, 1, 1, beq, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 20, 2, 0, beq, 0, -1 );
+
+ #-------------------------------------------------------------
+ # Test delay slot instructions not executed nor bypassed
+ #-------------------------------------------------------------
+
+ TEST_CASE( 21, x1, 3, \
+ li x1, 1; \
+ beq x0, x0, 1f; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+1: addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ )
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/bge.S b/tests/riscv-tests/rv32ui/bge.S
@@ -0,0 +1,76 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# bge.S
+#-----------------------------------------------------------------------------
+#
+# Test bge instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Branch tests
+ #-------------------------------------------------------------
+
+ # Each test checks both forward and backward branches
+
+ TEST_BR2_OP_TAKEN( 2, bge, 0, 0 );
+ TEST_BR2_OP_TAKEN( 3, bge, 1, 1 );
+ TEST_BR2_OP_TAKEN( 4, bge, -1, -1 );
+ TEST_BR2_OP_TAKEN( 5, bge, 1, 0 );
+ TEST_BR2_OP_TAKEN( 6, bge, 1, -1 );
+ TEST_BR2_OP_TAKEN( 7, bge, -1, -2 );
+
+ TEST_BR2_OP_NOTTAKEN( 8, bge, 0, 1 );
+ TEST_BR2_OP_NOTTAKEN( 9, bge, -1, 1 );
+ TEST_BR2_OP_NOTTAKEN( 10, bge, -2, -1 );
+ TEST_BR2_OP_NOTTAKEN( 11, bge, -2, 1 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_BR2_SRC12_BYPASS( 12, 0, 0, bge, -1, 0 );
+ TEST_BR2_SRC12_BYPASS( 13, 0, 1, bge, -1, 0 );
+ TEST_BR2_SRC12_BYPASS( 14, 0, 2, bge, -1, 0 );
+ TEST_BR2_SRC12_BYPASS( 15, 1, 0, bge, -1, 0 );
+ TEST_BR2_SRC12_BYPASS( 16, 1, 1, bge, -1, 0 );
+ TEST_BR2_SRC12_BYPASS( 17, 2, 0, bge, -1, 0 );
+
+ TEST_BR2_SRC12_BYPASS( 18, 0, 0, bge, -1, 0 );
+ TEST_BR2_SRC12_BYPASS( 19, 0, 1, bge, -1, 0 );
+ TEST_BR2_SRC12_BYPASS( 20, 0, 2, bge, -1, 0 );
+ TEST_BR2_SRC12_BYPASS( 21, 1, 0, bge, -1, 0 );
+ TEST_BR2_SRC12_BYPASS( 22, 1, 1, bge, -1, 0 );
+ TEST_BR2_SRC12_BYPASS( 23, 2, 0, bge, -1, 0 );
+
+ #-------------------------------------------------------------
+ # Test delay slot instructions not executed nor bypassed
+ #-------------------------------------------------------------
+
+ TEST_CASE( 24, x1, 3, \
+ li x1, 1; \
+ bge x1, x0, 1f; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+1: addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ )
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/bgeu.S b/tests/riscv-tests/rv32ui/bgeu.S
@@ -0,0 +1,76 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# bgeu.S
+#-----------------------------------------------------------------------------
+#
+# Test bgeu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Branch tests
+ #-------------------------------------------------------------
+
+ # Each test checks both forward and backward branches
+
+ TEST_BR2_OP_TAKEN( 2, bgeu, 0x00000000, 0x00000000 );
+ TEST_BR2_OP_TAKEN( 3, bgeu, 0x00000001, 0x00000001 );
+ TEST_BR2_OP_TAKEN( 4, bgeu, 0xffffffff, 0xffffffff );
+ TEST_BR2_OP_TAKEN( 5, bgeu, 0x00000001, 0x00000000 );
+ TEST_BR2_OP_TAKEN( 6, bgeu, 0xffffffff, 0xfffffffe );
+ TEST_BR2_OP_TAKEN( 7, bgeu, 0xffffffff, 0x00000000 );
+
+ TEST_BR2_OP_NOTTAKEN( 8, bgeu, 0x00000000, 0x00000001 );
+ TEST_BR2_OP_NOTTAKEN( 9, bgeu, 0xfffffffe, 0xffffffff );
+ TEST_BR2_OP_NOTTAKEN( 10, bgeu, 0x00000000, 0xffffffff );
+ TEST_BR2_OP_NOTTAKEN( 11, bgeu, 0x7fffffff, 0x80000000 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_BR2_SRC12_BYPASS( 12, 0, 0, bgeu, 0xefffffff, 0xf0000000 );
+ TEST_BR2_SRC12_BYPASS( 13, 0, 1, bgeu, 0xefffffff, 0xf0000000 );
+ TEST_BR2_SRC12_BYPASS( 14, 0, 2, bgeu, 0xefffffff, 0xf0000000 );
+ TEST_BR2_SRC12_BYPASS( 15, 1, 0, bgeu, 0xefffffff, 0xf0000000 );
+ TEST_BR2_SRC12_BYPASS( 16, 1, 1, bgeu, 0xefffffff, 0xf0000000 );
+ TEST_BR2_SRC12_BYPASS( 17, 2, 0, bgeu, 0xefffffff, 0xf0000000 );
+
+ TEST_BR2_SRC12_BYPASS( 18, 0, 0, bgeu, 0xefffffff, 0xf0000000 );
+ TEST_BR2_SRC12_BYPASS( 19, 0, 1, bgeu, 0xefffffff, 0xf0000000 );
+ TEST_BR2_SRC12_BYPASS( 20, 0, 2, bgeu, 0xefffffff, 0xf0000000 );
+ TEST_BR2_SRC12_BYPASS( 21, 1, 0, bgeu, 0xefffffff, 0xf0000000 );
+ TEST_BR2_SRC12_BYPASS( 22, 1, 1, bgeu, 0xefffffff, 0xf0000000 );
+ TEST_BR2_SRC12_BYPASS( 23, 2, 0, bgeu, 0xefffffff, 0xf0000000 );
+
+ #-------------------------------------------------------------
+ # Test delay slot instructions not executed nor bypassed
+ #-------------------------------------------------------------
+
+ TEST_CASE( 24, x1, 3, \
+ li x1, 1; \
+ bgeu x1, x0, 1f; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+1: addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ )
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/blt.S b/tests/riscv-tests/rv32ui/blt.S
@@ -0,0 +1,73 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# blt.S
+#-----------------------------------------------------------------------------
+#
+# Test blt instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Branch tests
+ #-------------------------------------------------------------
+
+ # Each test checks both forward and backward branches
+
+ TEST_BR2_OP_TAKEN( 2, blt, 0, 1 );
+ TEST_BR2_OP_TAKEN( 3, blt, -1, 1 );
+ TEST_BR2_OP_TAKEN( 4, blt, -2, -1 );
+
+ TEST_BR2_OP_NOTTAKEN( 5, blt, 1, 0 );
+ TEST_BR2_OP_NOTTAKEN( 6, blt, 1, -1 );
+ TEST_BR2_OP_NOTTAKEN( 7, blt, -1, -2 );
+ TEST_BR2_OP_NOTTAKEN( 8, blt, 1, -2 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_BR2_SRC12_BYPASS( 9, 0, 0, blt, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 10, 0, 1, blt, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 11, 0, 2, blt, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 12, 1, 0, blt, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 13, 1, 1, blt, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 14, 2, 0, blt, 0, -1 );
+
+ TEST_BR2_SRC12_BYPASS( 15, 0, 0, blt, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 16, 0, 1, blt, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 17, 0, 2, blt, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 18, 1, 0, blt, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 19, 1, 1, blt, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 20, 2, 0, blt, 0, -1 );
+
+ #-------------------------------------------------------------
+ # Test delay slot instructions not executed nor bypassed
+ #-------------------------------------------------------------
+
+ TEST_CASE( 21, x1, 3, \
+ li x1, 1; \
+ blt x0, x1, 1f; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+1: addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ )
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/bltu.S b/tests/riscv-tests/rv32ui/bltu.S
@@ -0,0 +1,73 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# bltu.S
+#-----------------------------------------------------------------------------
+#
+# Test bltu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Branch tests
+ #-------------------------------------------------------------
+
+ # Each test checks both forward and backward branches
+
+ TEST_BR2_OP_TAKEN( 2, bltu, 0x00000000, 0x00000001 );
+ TEST_BR2_OP_TAKEN( 3, bltu, 0xfffffffe, 0xffffffff );
+ TEST_BR2_OP_TAKEN( 4, bltu, 0x00000000, 0xffffffff );
+
+ TEST_BR2_OP_NOTTAKEN( 5, bltu, 0x00000001, 0x00000000 );
+ TEST_BR2_OP_NOTTAKEN( 6, bltu, 0xffffffff, 0xfffffffe );
+ TEST_BR2_OP_NOTTAKEN( 7, bltu, 0xffffffff, 0x00000000 );
+ TEST_BR2_OP_NOTTAKEN( 8, bltu, 0x80000000, 0x7fffffff );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_BR2_SRC12_BYPASS( 9, 0, 0, bltu, 0xf0000000, 0xefffffff );
+ TEST_BR2_SRC12_BYPASS( 10, 0, 1, bltu, 0xf0000000, 0xefffffff );
+ TEST_BR2_SRC12_BYPASS( 11, 0, 2, bltu, 0xf0000000, 0xefffffff );
+ TEST_BR2_SRC12_BYPASS( 12, 1, 0, bltu, 0xf0000000, 0xefffffff );
+ TEST_BR2_SRC12_BYPASS( 13, 1, 1, bltu, 0xf0000000, 0xefffffff );
+ TEST_BR2_SRC12_BYPASS( 14, 2, 0, bltu, 0xf0000000, 0xefffffff );
+
+ TEST_BR2_SRC12_BYPASS( 15, 0, 0, bltu, 0xf0000000, 0xefffffff );
+ TEST_BR2_SRC12_BYPASS( 16, 0, 1, bltu, 0xf0000000, 0xefffffff );
+ TEST_BR2_SRC12_BYPASS( 17, 0, 2, bltu, 0xf0000000, 0xefffffff );
+ TEST_BR2_SRC12_BYPASS( 18, 1, 0, bltu, 0xf0000000, 0xefffffff );
+ TEST_BR2_SRC12_BYPASS( 19, 1, 1, bltu, 0xf0000000, 0xefffffff );
+ TEST_BR2_SRC12_BYPASS( 20, 2, 0, bltu, 0xf0000000, 0xefffffff );
+
+ #-------------------------------------------------------------
+ # Test delay slot instructions not executed nor bypassed
+ #-------------------------------------------------------------
+
+ TEST_CASE( 21, x1, 3, \
+ li x1, 1; \
+ bltu x0, x1, 1f; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+1: addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ )
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/bne.S b/tests/riscv-tests/rv32ui/bne.S
@@ -0,0 +1,73 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# bne.S
+#-----------------------------------------------------------------------------
+#
+# Test bne instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Branch tests
+ #-------------------------------------------------------------
+
+ # Each test checks both forward and backward branches
+
+ TEST_BR2_OP_TAKEN( 2, bne, 0, 1 );
+ TEST_BR2_OP_TAKEN( 3, bne, 1, 0 );
+ TEST_BR2_OP_TAKEN( 4, bne, -1, 1 );
+ TEST_BR2_OP_TAKEN( 5, bne, 1, -1 );
+
+ TEST_BR2_OP_NOTTAKEN( 6, bne, 0, 0 );
+ TEST_BR2_OP_NOTTAKEN( 7, bne, 1, 1 );
+ TEST_BR2_OP_NOTTAKEN( 8, bne, -1, -1 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_BR2_SRC12_BYPASS( 9, 0, 0, bne, 0, 0 );
+ TEST_BR2_SRC12_BYPASS( 10, 0, 1, bne, 0, 0 );
+ TEST_BR2_SRC12_BYPASS( 11, 0, 2, bne, 0, 0 );
+ TEST_BR2_SRC12_BYPASS( 12, 1, 0, bne, 0, 0 );
+ TEST_BR2_SRC12_BYPASS( 13, 1, 1, bne, 0, 0 );
+ TEST_BR2_SRC12_BYPASS( 14, 2, 0, bne, 0, 0 );
+
+ TEST_BR2_SRC12_BYPASS( 15, 0, 0, bne, 0, 0 );
+ TEST_BR2_SRC12_BYPASS( 16, 0, 1, bne, 0, 0 );
+ TEST_BR2_SRC12_BYPASS( 17, 0, 2, bne, 0, 0 );
+ TEST_BR2_SRC12_BYPASS( 18, 1, 0, bne, 0, 0 );
+ TEST_BR2_SRC12_BYPASS( 19, 1, 1, bne, 0, 0 );
+ TEST_BR2_SRC12_BYPASS( 20, 2, 0, bne, 0, 0 );
+
+ #-------------------------------------------------------------
+ # Test delay slot instructions not executed nor bypassed
+ #-------------------------------------------------------------
+
+ TEST_CASE( 21, x1, 3, \
+ li x1, 1; \
+ bne x1, x0, 1f; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+1: addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ )
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/fence_i.S b/tests/riscv-tests/rv32ui/fence_i.S
@@ -0,0 +1,62 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fence_i.S
+#-----------------------------------------------------------------------------
+#
+# Test self-modifying code and the fence.i instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+li a3, 111
+lh a0, insn
+lh a1, insn+2
+
+# test I$ hit
+.align 6
+sh a0, 2f, t0
+sh a1, 2f+2, t0
+fence.i
+
+la a5, 2f
+jalr t1, a5, 0
+TEST_CASE( 2, a3, 444, nop )
+
+# test prefetcher hit
+li a4, 100
+1: addi a4, a4, -1
+bnez a4, 1b
+
+sh a0, 3f, t0
+sh a1, 3f+2, t0
+fence.i
+
+.align 6
+la a5, 3f
+jalr t1, a5, 0
+TEST_CASE( 3, a3, 777, nop )
+
+TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+insn:
+ addi a3, a3, 333
+
+2: addi a3, a3, 222
+jalr a5, t1, 0
+
+3: addi a3, a3, 555
+jalr a5, t1, 0
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/jal.S b/tests/riscv-tests/rv32ui/jal.S
@@ -0,0 +1,59 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# jal.S
+#-----------------------------------------------------------------------------
+#
+# Test jal instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Test 2: Basic test
+ #-------------------------------------------------------------
+
+test_2:
+ li TESTNUM, 2
+ li ra, 0
+
+ jal x4, target_2
+linkaddr_2:
+ nop
+ nop
+
+ j fail
+
+target_2:
+ la x2, linkaddr_2
+ bne x2, x4, fail
+
+ #-------------------------------------------------------------
+ # Test delay slot instructions not executed nor bypassed
+ #-------------------------------------------------------------
+
+ TEST_CASE( 3, ra, 3, \
+ li ra, 1; \
+ jal x0, 1f; \
+ addi ra, ra, 1; \
+ addi ra, ra, 1; \
+ addi ra, ra, 1; \
+ addi ra, ra, 1; \
+1: addi ra, ra, 1; \
+ addi ra, ra, 1; \
+ )
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/jalr.S b/tests/riscv-tests/rv32ui/jalr.S
@@ -0,0 +1,86 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# jalr.S
+#-----------------------------------------------------------------------------
+#
+# Test jalr instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Test 2: Basic test
+ #-------------------------------------------------------------
+
+test_2:
+ li TESTNUM, 2
+ li t0, 0
+ la t1, target_2
+
+ jalr t0, t1, 0
+linkaddr_2:
+ j fail
+
+target_2:
+ la t1, linkaddr_2
+ bne t0, t1, fail
+
+ #-------------------------------------------------------------
+ # Test 3: Basic test2, rs = rd
+ #-------------------------------------------------------------
+
+test_3:
+ li TESTNUM, 3
+ la t0, target_3
+
+ jalr t0, t0, 0
+linkaddr_3:
+ j fail
+
+target_3:
+ la t1, linkaddr_3
+ bne t0, t1, fail
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_JALR_SRC1_BYPASS( 4, 0, jalr );
+ TEST_JALR_SRC1_BYPASS( 5, 1, jalr );
+ TEST_JALR_SRC1_BYPASS( 6, 2, jalr );
+
+ #-------------------------------------------------------------
+ # Test delay slot instructions not executed nor bypassed
+ #-------------------------------------------------------------
+
+ .option push
+ .align 2
+ .option norvc
+ TEST_CASE( 7, t0, 4, \
+ li t0, 1; \
+ la t1, 1f; \
+ jr t1, -4; \
+ addi t0, t0, 1; \
+ addi t0, t0, 1; \
+ addi t0, t0, 1; \
+ addi t0, t0, 1; \
+1: addi t0, t0, 1; \
+ addi t0, t0, 1; \
+ )
+ .option pop
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/lb.S b/tests/riscv-tests/rv32ui/lb.S
@@ -0,0 +1,92 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# lb.S
+#-----------------------------------------------------------------------------
+#
+# Test lb instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Basic tests
+ #-------------------------------------------------------------
+
+ TEST_LD_OP( 2, lb, 0xffffffffffffffff, 0, tdat );
+ TEST_LD_OP( 3, lb, 0x0000000000000000, 1, tdat );
+ TEST_LD_OP( 4, lb, 0xfffffffffffffff0, 2, tdat );
+ TEST_LD_OP( 5, lb, 0x000000000000000f, 3, tdat );
+
+ # Test with negative offset
+
+ TEST_LD_OP( 6, lb, 0xffffffffffffffff, -3, tdat4 );
+ TEST_LD_OP( 7, lb, 0x0000000000000000, -2, tdat4 );
+ TEST_LD_OP( 8, lb, 0xfffffffffffffff0, -1, tdat4 );
+ TEST_LD_OP( 9, lb, 0x000000000000000f, 0, tdat4 );
+
+ # Test with a negative base
+
+ TEST_CASE( 10, x5, 0xffffffffffffffff, \
+ la x1, tdat; \
+ addi x1, x1, -32; \
+ lb x5, 32(x1); \
+ )
+
+ # Test with unaligned base
+
+ TEST_CASE( 11, x5, 0x0000000000000000, \
+ la x1, tdat; \
+ addi x1, x1, -6; \
+ lb x5, 7(x1); \
+ )
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_LD_DEST_BYPASS( 12, 0, lb, 0xfffffffffffffff0, 1, tdat2 );
+ TEST_LD_DEST_BYPASS( 13, 1, lb, 0x000000000000000f, 1, tdat3 );
+ TEST_LD_DEST_BYPASS( 14, 2, lb, 0x0000000000000000, 1, tdat1 );
+
+ TEST_LD_SRC1_BYPASS( 15, 0, lb, 0xfffffffffffffff0, 1, tdat2 );
+ TEST_LD_SRC1_BYPASS( 16, 1, lb, 0x000000000000000f, 1, tdat3 );
+ TEST_LD_SRC1_BYPASS( 17, 2, lb, 0x0000000000000000, 1, tdat1 );
+
+ #-------------------------------------------------------------
+ # Test write-after-write hazard
+ #-------------------------------------------------------------
+
+ TEST_CASE( 18, x2, 2, \
+ la x5, tdat; \
+ lb x2, 0(x5); \
+ li x2, 2; \
+ )
+
+ TEST_CASE( 19, x2, 2, \
+ la x5, tdat; \
+ lb x2, 0(x5); \
+ nop; \
+ li x2, 2; \
+ )
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+tdat:
+tdat1: .byte 0xff
+tdat2: .byte 0x00
+tdat3: .byte 0xf0
+tdat4: .byte 0x0f
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/lbu.S b/tests/riscv-tests/rv32ui/lbu.S
@@ -0,0 +1,92 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# lbu.S
+#-----------------------------------------------------------------------------
+#
+# Test lbu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Basic tests
+ #-------------------------------------------------------------
+
+ TEST_LD_OP( 2, lbu, 0x00000000000000ff, 0, tdat );
+ TEST_LD_OP( 3, lbu, 0x0000000000000000, 1, tdat );
+ TEST_LD_OP( 4, lbu, 0x00000000000000f0, 2, tdat );
+ TEST_LD_OP( 5, lbu, 0x000000000000000f, 3, tdat );
+
+ # Test with negative offset
+
+ TEST_LD_OP( 6, lbu, 0x00000000000000ff, -3, tdat4 );
+ TEST_LD_OP( 7, lbu, 0x0000000000000000, -2, tdat4 );
+ TEST_LD_OP( 8, lbu, 0x00000000000000f0, -1, tdat4 );
+ TEST_LD_OP( 9, lbu, 0x000000000000000f, 0, tdat4 );
+
+ # Test with a negative base
+
+ TEST_CASE( 10, x5, 0x00000000000000ff, \
+ la x1, tdat; \
+ addi x1, x1, -32; \
+ lbu x5, 32(x1); \
+ )
+
+ # Test with unaligned base
+
+ TEST_CASE( 11, x5, 0x0000000000000000, \
+ la x1, tdat; \
+ addi x1, x1, -6; \
+ lbu x5, 7(x1); \
+ )
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_LD_DEST_BYPASS( 12, 0, lbu, 0x00000000000000f0, 1, tdat2 );
+ TEST_LD_DEST_BYPASS( 13, 1, lbu, 0x000000000000000f, 1, tdat3 );
+ TEST_LD_DEST_BYPASS( 14, 2, lbu, 0x0000000000000000, 1, tdat1 );
+
+ TEST_LD_SRC1_BYPASS( 15, 0, lbu, 0x00000000000000f0, 1, tdat2 );
+ TEST_LD_SRC1_BYPASS( 16, 1, lbu, 0x000000000000000f, 1, tdat3 );
+ TEST_LD_SRC1_BYPASS( 17, 2, lbu, 0x0000000000000000, 1, tdat1 );
+
+ #-------------------------------------------------------------
+ # Test write-after-write hazard
+ #-------------------------------------------------------------
+
+ TEST_CASE( 18, x2, 2, \
+ la x5, tdat; \
+ lbu x2, 0(x5); \
+ li x2, 2; \
+ )
+
+ TEST_CASE( 19, x2, 2, \
+ la x5, tdat; \
+ lbu x2, 0(x5); \
+ nop; \
+ li x2, 2; \
+ )
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+tdat:
+tdat1: .byte 0xff
+tdat2: .byte 0x00
+tdat3: .byte 0xf0
+tdat4: .byte 0x0f
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/ld.S b/tests/riscv-tests/rv32ui/ld.S
@@ -0,0 +1,92 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# ld.S
+#-----------------------------------------------------------------------------
+#
+# Test ld instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Basic tests
+ #-------------------------------------------------------------
+
+ TEST_LD_OP( 2, ld, 0x00ff00ff00ff00ff, 0, tdat );
+ TEST_LD_OP( 3, ld, 0xff00ff00ff00ff00, 8, tdat );
+ TEST_LD_OP( 4, ld, 0x0ff00ff00ff00ff0, 16, tdat );
+ TEST_LD_OP( 5, ld, 0xf00ff00ff00ff00f, 24, tdat );
+
+ # Test with negative offset
+
+ TEST_LD_OP( 6, ld, 0x00ff00ff00ff00ff, -24, tdat4 );
+ TEST_LD_OP( 7, ld, 0xff00ff00ff00ff00, -16, tdat4 );
+ TEST_LD_OP( 8, ld, 0x0ff00ff00ff00ff0, -8, tdat4 );
+ TEST_LD_OP( 9, ld, 0xf00ff00ff00ff00f, 0, tdat4 );
+
+ # Test with a negative base
+
+ TEST_CASE( 10, x5, 0x00ff00ff00ff00ff, \
+ la x1, tdat; \
+ addi x1, x1, -32; \
+ ld x5, 32(x1); \
+ )
+
+ # Test with unaligned base
+
+ TEST_CASE( 11, x5, 0xff00ff00ff00ff00, \
+ la x1, tdat; \
+ addi x1, x1, -3; \
+ ld x5, 11(x1); \
+ )
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_LD_DEST_BYPASS( 12, 0, ld, 0x0ff00ff00ff00ff0, 8, tdat2 );
+ TEST_LD_DEST_BYPASS( 13, 1, ld, 0xf00ff00ff00ff00f, 8, tdat3 );
+ TEST_LD_DEST_BYPASS( 14, 2, ld, 0xff00ff00ff00ff00, 8, tdat1 );
+
+ TEST_LD_SRC1_BYPASS( 15, 0, ld, 0x0ff00ff00ff00ff0, 8, tdat2 );
+ TEST_LD_SRC1_BYPASS( 16, 1, ld, 0xf00ff00ff00ff00f, 8, tdat3 );
+ TEST_LD_SRC1_BYPASS( 17, 2, ld, 0xff00ff00ff00ff00, 8, tdat1 );
+
+ #-------------------------------------------------------------
+ # Test write-after-write hazard
+ #-------------------------------------------------------------
+
+ TEST_CASE( 18, x2, 2, \
+ la x5, tdat; \
+ ld x2, 0(x5); \
+ li x2, 2; \
+ )
+
+ TEST_CASE( 19, x2, 2, \
+ la x5, tdat; \
+ ld x2, 0(x5); \
+ nop; \
+ li x2, 2; \
+ )
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+tdat:
+tdat1: .dword 0x00ff00ff00ff00ff
+tdat2: .dword 0xff00ff00ff00ff00
+tdat3: .dword 0x0ff00ff00ff00ff0
+tdat4: .dword 0xf00ff00ff00ff00f
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/ld_st.S b/tests/riscv-tests/rv32ui/ld_st.S
@@ -0,0 +1,130 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# ld_st.S
+#-----------------------------------------------------------------------------
+#
+# Test load and store instructions
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Bypassing Tests
+ #-------------------------------------------------------------
+
+ # Test sb and lb (signed byte)
+ TEST_LD_ST_BYPASS(2, lb, sb, 0xffffffffffffffdd, 0, tdat );
+ TEST_LD_ST_BYPASS(3, lb, sb, 0xffffffffffffffcd, 1, tdat );
+ TEST_LD_ST_BYPASS(4, lb, sb, 0xffffffffffffffcc, 2, tdat );
+ TEST_LD_ST_BYPASS(5, lb, sb, 0xffffffffffffffbc, 3, tdat );
+ TEST_LD_ST_BYPASS(6, lb, sb, 0xffffffffffffffbb, 4, tdat );
+ TEST_LD_ST_BYPASS(7, lb, sb, 0xffffffffffffffab, 5, tdat );
+
+ TEST_LD_ST_BYPASS(8, lb, sb, 0x33, 0, tdat );
+ TEST_LD_ST_BYPASS(9, lb, sb, 0x23, 1, tdat );
+ TEST_LD_ST_BYPASS(10, lb, sb, 0x22, 2, tdat );
+ TEST_LD_ST_BYPASS(11, lb, sb, 0x12, 3, tdat );
+ TEST_LD_ST_BYPASS(12, lb, sb, 0x11, 4, tdat );
+ TEST_LD_ST_BYPASS(13, lb, sb, 0x01, 5, tdat );
+
+ # Test sb and lbu (unsigned byte)
+ TEST_LD_ST_BYPASS(14, lbu, sb, 0x33, 0, tdat );
+ TEST_LD_ST_BYPASS(15, lbu, sb, 0x23, 1, tdat );
+ TEST_LD_ST_BYPASS(16, lbu, sb, 0x22, 2, tdat );
+ TEST_LD_ST_BYPASS(17, lbu, sb, 0x12, 3, tdat );
+ TEST_LD_ST_BYPASS(18, lbu, sb, 0x11, 4, tdat );
+ TEST_LD_ST_BYPASS(19, lbu, sb, 0x01, 5, tdat );
+
+ # Test sw and lw (signed word)
+ TEST_LD_ST_BYPASS(20, lw, sw, 0xffffffffaabbccdd, 0, tdat );
+ TEST_LD_ST_BYPASS(21, lw, sw, 0xffffffffdaabbccd, 4, tdat );
+ TEST_LD_ST_BYPASS(22, lw, sw, 0xffffffffddaabbcc, 8, tdat );
+ TEST_LD_ST_BYPASS(23, lw, sw, 0xffffffffcddaabbc, 12, tdat );
+ TEST_LD_ST_BYPASS(24, lw, sw, 0xffffffffccddaabb, 16, tdat );
+ TEST_LD_ST_BYPASS(25, lw, sw, 0xffffffffbccddaab, 20, tdat );
+
+ TEST_LD_ST_BYPASS(26, lw, sw, 0x00112233, 0, tdat );
+ TEST_LD_ST_BYPASS(27, lw, sw, 0x30011223, 4, tdat );
+ TEST_LD_ST_BYPASS(28, lw, sw, 0x33001122, 8, tdat );
+ TEST_LD_ST_BYPASS(29, lw, sw, 0x23300112, 12, tdat );
+ TEST_LD_ST_BYPASS(30, lw, sw, 0x22330011, 16, tdat );
+ TEST_LD_ST_BYPASS(31, lw, sw, 0x12233001, 20, tdat );
+
+ # Test sh and lh (signed halfword)
+ TEST_LD_ST_BYPASS(32, lh, sh, 0xffffffffffffccdd, 0, tdat );
+ TEST_LD_ST_BYPASS(33, lh, sh, 0xffffffffffffbccd, 2, tdat );
+ TEST_LD_ST_BYPASS(34, lh, sh, 0xffffffffffffbbcc, 4, tdat );
+ TEST_LD_ST_BYPASS(35, lh, sh, 0xffffffffffffabbc, 6, tdat );
+ TEST_LD_ST_BYPASS(36, lh, sh, 0xffffffffffffaabb, 8, tdat );
+ TEST_LD_ST_BYPASS(37, lh, sh, 0xffffffffffffdaab, 10, tdat );
+
+ TEST_LD_ST_BYPASS(38, lh, sh, 0x2233, 0, tdat );
+ TEST_LD_ST_BYPASS(39, lh, sh, 0x1223, 2, tdat );
+ TEST_LD_ST_BYPASS(40, lh, sh, 0x1122, 4, tdat );
+ TEST_LD_ST_BYPASS(41, lh, sh, 0x0112, 6, tdat );
+ TEST_LD_ST_BYPASS(42, lh, sh, 0x0011, 8, tdat );
+ TEST_LD_ST_BYPASS(43, lh, sh, 0x3001, 10, tdat );
+
+ # Test sh and lhu (unsigned halfword)
+ TEST_LD_ST_BYPASS(44, lhu, sh, 0x2233, 0, tdat );
+ TEST_LD_ST_BYPASS(45, lhu, sh, 0x1223, 2, tdat );
+ TEST_LD_ST_BYPASS(46, lhu, sh, 0x1122, 4, tdat );
+ TEST_LD_ST_BYPASS(47, lhu, sh, 0x0112, 6, tdat );
+ TEST_LD_ST_BYPASS(48, lhu, sh, 0x0011, 8, tdat );
+ TEST_LD_ST_BYPASS(49, lhu, sh, 0x3001, 10, tdat );
+
+ # RV64-specific tests for ld, sd, and lwu
+#if __riscv_xlen == 64
+ # Test sd and ld (doubleword)
+ TEST_LD_ST_BYPASS(50, ld, sd, 0x0011223344556677, 0, tdat );
+ TEST_LD_ST_BYPASS(51, ld, sd, 0x1122334455667788, 8, tdat );
+ TEST_LD_ST_BYPASS(52, ld, sd, 0x2233445566778899, 16, tdat );
+ TEST_LD_ST_BYPASS(53, ld, sd, 0xabbccdd, 0, tdat );
+ TEST_LD_ST_BYPASS(54, ld, sd, 0xaabbccd, 8, tdat );
+ TEST_LD_ST_BYPASS(55, ld, sd, 0xdaabbcc, 16, tdat );
+ TEST_LD_ST_BYPASS(56, ld, sd, 0xddaabbc, 24, tdat );
+ TEST_LD_ST_BYPASS(57, ld, sd, 0xcddaabb, 32, tdat );
+ TEST_LD_ST_BYPASS(58, ld, sd, 0xccddaab, 40, tdat );
+
+ TEST_LD_ST_BYPASS(59, ld, sd, 0x00112233, 0, tdat );
+ TEST_LD_ST_BYPASS(60, ld, sd, 0x30011223, 8, tdat );
+ TEST_LD_ST_BYPASS(61, ld, sd, 0x33001122, 16, tdat );
+ TEST_LD_ST_BYPASS(62, ld, sd, 0x23300112, 24, tdat );
+ TEST_LD_ST_BYPASS(63, ld, sd, 0x22330011, 32, tdat );
+ TEST_LD_ST_BYPASS(64, ld, sd, 0x12233001, 40, tdat );
+
+ # Test sw and lwu (unsigned word)
+ TEST_LD_ST_BYPASS(65, lwu, sw, 0x00112233, 0, tdat );
+ TEST_LD_ST_BYPASS(66, lwu, sw, 0x33001122, 8, tdat );
+ TEST_LD_ST_BYPASS(67, lwu, sw, 0x30011223, 4, tdat );
+ TEST_LD_ST_BYPASS(68, lwu, sw, 0x23300112, 12, tdat );
+ TEST_LD_ST_BYPASS(69, lwu, sw, 0x22330011, 16, tdat );
+ TEST_LD_ST_BYPASS(70, lwu, sw, 0x12233001, 20, tdat );
+#endif
+
+ li a0, 0xef # Immediate load for manual store test
+ la a1, tdat # Load address of tdat
+ sb a0, 3(a1) # Store byte at offset 3 of tdat
+ lb a2, 3(a1) # Load byte back for verification
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+tdat:
+ .rept 20
+ .word 0xdeadbeef
+ .endr
+
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/lh.S b/tests/riscv-tests/rv32ui/lh.S
@@ -0,0 +1,92 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# lh.S
+#-----------------------------------------------------------------------------
+#
+# Test lh instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Basic tests
+ #-------------------------------------------------------------
+
+ TEST_LD_OP( 2, lh, 0x00000000000000ff, 0, tdat );
+ TEST_LD_OP( 3, lh, 0xffffffffffffff00, 2, tdat );
+ TEST_LD_OP( 4, lh, 0x0000000000000ff0, 4, tdat );
+ TEST_LD_OP( 5, lh, 0xfffffffffffff00f, 6, tdat );
+
+ # Test with negative offset
+
+ TEST_LD_OP( 6, lh, 0x00000000000000ff, -6, tdat4 );
+ TEST_LD_OP( 7, lh, 0xffffffffffffff00, -4, tdat4 );
+ TEST_LD_OP( 8, lh, 0x0000000000000ff0, -2, tdat4 );
+ TEST_LD_OP( 9, lh, 0xfffffffffffff00f, 0, tdat4 );
+
+ # Test with a negative base
+
+ TEST_CASE( 10, x5, 0x00000000000000ff, \
+ la x1, tdat; \
+ addi x1, x1, -32; \
+ lh x5, 32(x1); \
+ )
+
+ # Test with unaligned base
+
+ TEST_CASE( 11, x5, 0xffffffffffffff00, \
+ la x1, tdat; \
+ addi x1, x1, -5; \
+ lh x5, 7(x1); \
+ )
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_LD_DEST_BYPASS( 12, 0, lh, 0x0000000000000ff0, 2, tdat2 );
+ TEST_LD_DEST_BYPASS( 13, 1, lh, 0xfffffffffffff00f, 2, tdat3 );
+ TEST_LD_DEST_BYPASS( 14, 2, lh, 0xffffffffffffff00, 2, tdat1 );
+
+ TEST_LD_SRC1_BYPASS( 15, 0, lh, 0x0000000000000ff0, 2, tdat2 );
+ TEST_LD_SRC1_BYPASS( 16, 1, lh, 0xfffffffffffff00f, 2, tdat3 );
+ TEST_LD_SRC1_BYPASS( 17, 2, lh, 0xffffffffffffff00, 2, tdat1 );
+
+ #-------------------------------------------------------------
+ # Test write-after-write hazard
+ #-------------------------------------------------------------
+
+ TEST_CASE( 18, x2, 2, \
+ la x5, tdat; \
+ lh x2, 0(x5); \
+ li x2, 2; \
+ )
+
+ TEST_CASE( 19, x2, 2, \
+ la x5, tdat; \
+ lh x2, 0(x5); \
+ nop; \
+ li x2, 2; \
+ )
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+tdat:
+tdat1: .half 0x00ff
+tdat2: .half 0xff00
+tdat3: .half 0x0ff0
+tdat4: .half 0xf00f
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/lhu.S b/tests/riscv-tests/rv32ui/lhu.S
@@ -0,0 +1,92 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# lhu.S
+#-----------------------------------------------------------------------------
+#
+# Test lhu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Basic tests
+ #-------------------------------------------------------------
+
+ TEST_LD_OP( 2, lhu, 0x00000000000000ff, 0, tdat );
+ TEST_LD_OP( 3, lhu, 0x000000000000ff00, 2, tdat );
+ TEST_LD_OP( 4, lhu, 0x0000000000000ff0, 4, tdat );
+ TEST_LD_OP( 5, lhu, 0x000000000000f00f, 6, tdat );
+
+ # Test with negative offset
+
+ TEST_LD_OP( 6, lhu, 0x00000000000000ff, -6, tdat4 );
+ TEST_LD_OP( 7, lhu, 0x000000000000ff00, -4, tdat4 );
+ TEST_LD_OP( 8, lhu, 0x0000000000000ff0, -2, tdat4 );
+ TEST_LD_OP( 9, lhu, 0x000000000000f00f, 0, tdat4 );
+
+ # Test with a negative base
+
+ TEST_CASE( 10, x5, 0x00000000000000ff, \
+ la x1, tdat; \
+ addi x1, x1, -32; \
+ lhu x5, 32(x1); \
+ )
+
+ # Test with unaligned base
+
+ TEST_CASE( 11, x5, 0x000000000000ff00, \
+ la x1, tdat; \
+ addi x1, x1, -5; \
+ lhu x5, 7(x1); \
+ )
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_LD_DEST_BYPASS( 12, 0, lhu, 0x0000000000000ff0, 2, tdat2 );
+ TEST_LD_DEST_BYPASS( 13, 1, lhu, 0x000000000000f00f, 2, tdat3 );
+ TEST_LD_DEST_BYPASS( 14, 2, lhu, 0x000000000000ff00, 2, tdat1 );
+
+ TEST_LD_SRC1_BYPASS( 15, 0, lhu, 0x0000000000000ff0, 2, tdat2 );
+ TEST_LD_SRC1_BYPASS( 16, 1, lhu, 0x000000000000f00f, 2, tdat3 );
+ TEST_LD_SRC1_BYPASS( 17, 2, lhu, 0x000000000000ff00, 2, tdat1 );
+
+ #-------------------------------------------------------------
+ # Test write-after-write hazard
+ #-------------------------------------------------------------
+
+ TEST_CASE( 18, x2, 2, \
+ la x5, tdat; \
+ lhu x2, 0(x5); \
+ li x2, 2; \
+ )
+
+ TEST_CASE( 19, x2, 2, \
+ la x5, tdat; \
+ lhu x2, 0(x5); \
+ nop; \
+ li x2, 2; \
+ )
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+tdat:
+tdat1: .half 0x00ff
+tdat2: .half 0xff00
+tdat3: .half 0x0ff0
+tdat4: .half 0xf00f
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/lui.S b/tests/riscv-tests/rv32ui/lui.S
@@ -0,0 +1,36 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# lui.S
+#-----------------------------------------------------------------------------
+#
+# Test lui instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Basic tests
+ #-------------------------------------------------------------
+
+ TEST_CASE( 2, x1, 0x0000000000000000, lui x1, 0x00000 );
+ TEST_CASE( 3, x1, 0xfffffffffffff800, lui x1, 0xfffff;sra x1,x1,1);
+ TEST_CASE( 4, x1, 0x00000000000007ff, lui x1, 0x7ffff;sra x1,x1,20);
+ TEST_CASE( 5, x1, 0xfffffffffffff800, lui x1, 0x80000;sra x1,x1,20);
+
+ TEST_CASE( 6, x0, 0, lui x0, 0x80000 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/lw.S b/tests/riscv-tests/rv32ui/lw.S
@@ -0,0 +1,92 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# lw.S
+#-----------------------------------------------------------------------------
+#
+# Test lw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Basic tests
+ #-------------------------------------------------------------
+
+ TEST_LD_OP( 2, lw, 0x0000000000ff00ff, 0, tdat );
+ TEST_LD_OP( 3, lw, 0xffffffffff00ff00, 4, tdat );
+ TEST_LD_OP( 4, lw, 0x000000000ff00ff0, 8, tdat );
+ TEST_LD_OP( 5, lw, 0xfffffffff00ff00f, 12, tdat );
+
+ # Test with negative offset
+
+ TEST_LD_OP( 6, lw, 0x0000000000ff00ff, -12, tdat4 );
+ TEST_LD_OP( 7, lw, 0xffffffffff00ff00, -8, tdat4 );
+ TEST_LD_OP( 8, lw, 0x000000000ff00ff0, -4, tdat4 );
+ TEST_LD_OP( 9, lw, 0xfffffffff00ff00f, 0, tdat4 );
+
+ # Test with a negative base
+
+ TEST_CASE( 10, x5, 0x0000000000ff00ff, \
+ la x1, tdat; \
+ addi x1, x1, -32; \
+ lw x5, 32(x1); \
+ )
+
+ # Test with unaligned base
+
+ TEST_CASE( 11, x5, 0xffffffffff00ff00, \
+ la x1, tdat; \
+ addi x1, x1, -3; \
+ lw x5, 7(x1); \
+ )
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_LD_DEST_BYPASS( 12, 0, lw, 0x000000000ff00ff0, 4, tdat2 );
+ TEST_LD_DEST_BYPASS( 13, 1, lw, 0xfffffffff00ff00f, 4, tdat3 );
+ TEST_LD_DEST_BYPASS( 14, 2, lw, 0xffffffffff00ff00, 4, tdat1 );
+
+ TEST_LD_SRC1_BYPASS( 15, 0, lw, 0x000000000ff00ff0, 4, tdat2 );
+ TEST_LD_SRC1_BYPASS( 16, 1, lw, 0xfffffffff00ff00f, 4, tdat3 );
+ TEST_LD_SRC1_BYPASS( 17, 2, lw, 0xffffffffff00ff00, 4, tdat1 );
+
+ #-------------------------------------------------------------
+ # Test write-after-write hazard
+ #-------------------------------------------------------------
+
+ TEST_CASE( 18, x2, 2, \
+ la x5, tdat; \
+ lw x2, 0(x5); \
+ li x2, 2; \
+ )
+
+ TEST_CASE( 19, x2, 2, \
+ la x5, tdat; \
+ lw x2, 0(x5); \
+ nop; \
+ li x2, 2; \
+ )
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+tdat:
+tdat1: .word 0x00ff00ff
+tdat2: .word 0xff00ff00
+tdat3: .word 0x0ff00ff0
+tdat4: .word 0xf00ff00f
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/lwu.S b/tests/riscv-tests/rv32ui/lwu.S
@@ -0,0 +1,92 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# lwu.S
+#-----------------------------------------------------------------------------
+#
+# Test lwu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Basic tests
+ #-------------------------------------------------------------
+
+ TEST_LD_OP( 2, lwu, 0x0000000000ff00ff, 0, tdat );
+ TEST_LD_OP( 3, lwu, 0x00000000ff00ff00, 4, tdat );
+ TEST_LD_OP( 4, lwu, 0x000000000ff00ff0, 8, tdat );
+ TEST_LD_OP( 5, lwu, 0x00000000f00ff00f, 12, tdat );
+
+ # Test with negative offset
+
+ TEST_LD_OP( 6, lwu, 0x0000000000ff00ff, -12, tdat4 );
+ TEST_LD_OP( 7, lwu, 0x00000000ff00ff00, -8, tdat4 );
+ TEST_LD_OP( 8, lwu, 0x000000000ff00ff0, -4, tdat4 );
+ TEST_LD_OP( 9, lwu, 0x00000000f00ff00f, 0, tdat4 );
+
+ # Test with a negative base
+
+ TEST_CASE( 10, x5, 0x0000000000ff00ff, \
+ la x1, tdat; \
+ addi x1, x1, -32; \
+ lwu x5, 32(x1); \
+ )
+
+ # Test with unaligned base
+
+ TEST_CASE( 11, x5, 0x00000000ff00ff00, \
+ la x1, tdat; \
+ addi x1, x1, -3; \
+ lwu x5, 7(x1); \
+ )
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_LD_DEST_BYPASS( 12, 0, lwu, 0x000000000ff00ff0, 4, tdat2 );
+ TEST_LD_DEST_BYPASS( 13, 1, lwu, 0x00000000f00ff00f, 4, tdat3 );
+ TEST_LD_DEST_BYPASS( 14, 2, lwu, 0x00000000ff00ff00, 4, tdat1 );
+
+ TEST_LD_SRC1_BYPASS( 15, 0, lwu, 0x000000000ff00ff0, 4, tdat2 );
+ TEST_LD_SRC1_BYPASS( 16, 1, lwu, 0x00000000f00ff00f, 4, tdat3 );
+ TEST_LD_SRC1_BYPASS( 17, 2, lwu, 0x00000000ff00ff00, 4, tdat1 );
+
+ #-------------------------------------------------------------
+ # Test write-after-write hazard
+ #-------------------------------------------------------------
+
+ TEST_CASE( 18, x2, 2, \
+ la x5, tdat; \
+ lwu x2, 0(x5); \
+ li x2, 2; \
+ )
+
+ TEST_CASE( 19, x2, 2, \
+ la x5, tdat; \
+ lwu x2, 0(x5); \
+ nop; \
+ li x2, 2; \
+ )
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+tdat:
+tdat1: .word 0x00ff00ff
+tdat2: .word 0xff00ff00
+tdat3: .word 0x0ff00ff0
+tdat4: .word 0xf00ff00f
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/ma_data.S b/tests/riscv-tests/rv32ui/ma_data.S
@@ -0,0 +1,383 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# ma_data.S
+#-----------------------------------------------------------------------------
+#
+# Test misaligned ld/st data.
+# Based on rv64mi-ma_addr.S
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ la s0, data
+
+#define SEXT(x, n) ((-((x) >> ((n)-1)) << (n)) | ((x) & ((1 << (n))-1)))
+
+/* Check that a misaligned load reads the correct value. */
+#define MISALIGNED_LOAD_TEST(testnum, insn, base, offset, res) \
+ li TESTNUM, testnum; \
+ li t1, res; \
+ insn t2, offset(base); \
+ bne t1, t2, fail; \
+1:
+
+# within quadword
+ MISALIGNED_LOAD_TEST(1, lh, s0, 1, SEXT(0x0201, 16))
+ MISALIGNED_LOAD_TEST(2, lhu, s0, 1, 0x0201)
+ MISALIGNED_LOAD_TEST(3, lw, s0, 1, SEXT(0x04030201, 32))
+ MISALIGNED_LOAD_TEST(4, lw, s0, 2, SEXT(0x05040302, 32))
+ MISALIGNED_LOAD_TEST(5, lw, s0, 3, SEXT(0x06050403, 32))
+
+#if __riscv_xlen == 64
+ MISALIGNED_LOAD_TEST(6, lwu, s0, 1, 0x04030201)
+ MISALIGNED_LOAD_TEST(7, lwu, s0, 2, 0x05040302)
+ MISALIGNED_LOAD_TEST(8, lwu, s0, 3, 0x06050403)
+
+ MISALIGNED_LOAD_TEST(9, ld, s0, 1, 0x0807060504030201)
+ MISALIGNED_LOAD_TEST(10, ld, s0, 2, 0x0908070605040302)
+ MISALIGNED_LOAD_TEST(11, ld, s0, 3, 0x0a09080706050403)
+ MISALIGNED_LOAD_TEST(12, ld, s0, 4, 0x0b0a090807060504)
+ MISALIGNED_LOAD_TEST(13, ld, s0, 5, 0x0c0b0a0908070605)
+ MISALIGNED_LOAD_TEST(14, ld, s0, 6, 0x0d0c0b0a09080706)
+ MISALIGNED_LOAD_TEST(15, ld, s0, 7, 0x0e0d0c0b0a090807)
+#endif
+
+# octword crossing
+ MISALIGNED_LOAD_TEST(16, lh, s0, 31, SEXT(0x201f, 16))
+ MISALIGNED_LOAD_TEST(17, lhu, s0, 31, 0x201f)
+ MISALIGNED_LOAD_TEST(18, lw, s0, 29, SEXT(0x201f1e1d, 32))
+ MISALIGNED_LOAD_TEST(19, lw, s0, 30, SEXT(0x21201f1e, 32))
+ MISALIGNED_LOAD_TEST(20, lw, s0, 31, SEXT(0x2221201f, 32))
+
+#if __riscv_xlen == 64
+ MISALIGNED_LOAD_TEST(21, lwu, s0, 29, 0x201f1e1d)
+ MISALIGNED_LOAD_TEST(22, lwu, s0, 30, 0x21201f1e)
+ MISALIGNED_LOAD_TEST(23, lwu, s0, 31, 0x2221201f)
+
+ MISALIGNED_LOAD_TEST(24, ld, s0, 25, 0x201f1e1d1c1b1a19)
+ MISALIGNED_LOAD_TEST(25, ld, s0, 26, 0x21201f1e1d1c1b1a)
+ MISALIGNED_LOAD_TEST(26, ld, s0, 27, 0x2221201f1e1d1c1b)
+ MISALIGNED_LOAD_TEST(27, ld, s0, 28, 0x232221201f1e1d1c)
+ MISALIGNED_LOAD_TEST(28, ld, s0, 29, 0x24232221201f1e1d)
+ MISALIGNED_LOAD_TEST(29, ld, s0, 30, 0x2524232221201f1e)
+ MISALIGNED_LOAD_TEST(30, ld, s0, 31, 0x262524232221201f)
+#endif
+
+# cacheline crossing
+ MISALIGNED_LOAD_TEST(31, lh, s0, 63, SEXT(0x403f, 16))
+ MISALIGNED_LOAD_TEST(32, lhu, s0, 63, 0x403f)
+ MISALIGNED_LOAD_TEST(33, lw, s0, 61, SEXT(0x403f3e3d, 32))
+ MISALIGNED_LOAD_TEST(34, lw, s0, 62, SEXT(0x41403f3e, 32))
+ MISALIGNED_LOAD_TEST(35, lw, s0, 63, SEXT(0x4241403f, 32))
+
+#if __riscv_xlen == 64
+ MISALIGNED_LOAD_TEST(36, lwu, s0, 61, 0x403f3e3d)
+ MISALIGNED_LOAD_TEST(37, lwu, s0, 62, 0x41403f3e)
+ MISALIGNED_LOAD_TEST(38, lwu, s0, 63, 0x4241403f)
+
+ MISALIGNED_LOAD_TEST(39, ld, s0, 57, 0x403f3e3d3c3b3a39)
+ MISALIGNED_LOAD_TEST(40, ld, s0, 58, 0x41403f3e3d3c3b3a)
+ MISALIGNED_LOAD_TEST(41, ld, s0, 59, 0x4241403f3e3d3c3b)
+ MISALIGNED_LOAD_TEST(42, ld, s0, 60, 0x434241403f3e3d3c)
+ MISALIGNED_LOAD_TEST(43, ld, s0, 61, 0x44434241403f3e3d)
+ MISALIGNED_LOAD_TEST(44, ld, s0, 62, 0x4544434241403f3e)
+ MISALIGNED_LOAD_TEST(45, ld, s0, 63, 0x464544434241403f)
+#endif
+
+
+/* Check that a misaligned store writes the correct value. */
+#define MISALIGNED_STORE_TEST(testnum, st_insn, ld_insn, base, offset, st_data) \
+ li TESTNUM, testnum; \
+ li t1, st_data; \
+ st_insn t1, offset(base); \
+ ld_insn t2, offset(base); \
+ bne t1, t2, fail; \
+1:
+
+# within quadword
+ MISALIGNED_STORE_TEST(46, sh, lh, s0, 1, SEXT(0x8180, 16))
+ MISALIGNED_STORE_TEST(47, sh, lhu, s0, 1, 0x8382)
+ MISALIGNED_STORE_TEST(48, sw, lw, s0, 1, SEXT(0x87868584, 32))
+ MISALIGNED_STORE_TEST(49, sw, lw, s0, 2, SEXT(0x8b8a8988, 32))
+ MISALIGNED_STORE_TEST(50, sw, lw, s0, 3, SEXT(0x8f8e8d8c, 32))
+
+#if __riscv_xlen == 64
+ MISALIGNED_STORE_TEST(51, sw, lwu, s0, 1, 0x93929190)
+ MISALIGNED_STORE_TEST(52, sw, lwu, s0, 2, 0x97969594)
+ MISALIGNED_STORE_TEST(53, sw, lwu, s0, 3, 0x9b9a9998)
+
+ MISALIGNED_STORE_TEST(54, sd, ld, s0, 1, 0xa3a2a1a09f9e9d9c)
+ MISALIGNED_STORE_TEST(55, sd, ld, s0, 2, 0xabaaa9a8a7a6a5a4)
+ MISALIGNED_STORE_TEST(56, sd, ld, s0, 3, 0xb3b2b1b0afaeadac)
+ MISALIGNED_STORE_TEST(57, sd, ld, s0, 4, 0xbbbab9b8b7b6b5b4)
+ MISALIGNED_STORE_TEST(58, sd, ld, s0, 5, 0xc3c2c1c0bfbebdbc)
+ MISALIGNED_STORE_TEST(59, sd, ld, s0, 6, 0xcbcac9c8c7c6c5c4)
+ MISALIGNED_STORE_TEST(60, sd, ld, s0, 7, 0xd3d2d1d0cfcecdcc)
+#endif
+
+# octword crossing
+ MISALIGNED_STORE_TEST(61, sh, lh, s0, 31, SEXT(0xd5d4, 16))
+ MISALIGNED_STORE_TEST(62, sh, lhu, s0, 31, 0xd7d6)
+ MISALIGNED_STORE_TEST(63, sw, lw, s0, 29, SEXT(0xdbdad9d8, 32))
+ MISALIGNED_STORE_TEST(64, sw, lw, s0, 30, SEXT(0xdfdedddc, 32))
+ MISALIGNED_STORE_TEST(65, sw, lw, s0, 31, SEXT(0xe3e2e1e0, 32))
+
+#if __riscv_xlen == 64
+ MISALIGNED_STORE_TEST(66, sw, lwu, s0, 29, 0xe7e6e5e4)
+ MISALIGNED_STORE_TEST(67, sw, lwu, s0, 30, 0xebeae9e8)
+ MISALIGNED_STORE_TEST(68, sw, lwu, s0, 31, 0xefeeedec)
+
+ MISALIGNED_STORE_TEST(69, sd, ld, s0, 25, 0xf7f6f5f4f3f2f1f0)
+ MISALIGNED_STORE_TEST(70, sd, ld, s0, 26, 0xfffefdfcfbfaf9f8)
+ MISALIGNED_STORE_TEST(71, sd, ld, s0, 27, 0x0706050403020100)
+ MISALIGNED_STORE_TEST(72, sd, ld, s0, 28, 0x0f0e0d0c0b0a0908)
+ MISALIGNED_STORE_TEST(73, sd, ld, s0, 29, 0x1716151413121110)
+ MISALIGNED_STORE_TEST(74, sd, ld, s0, 30, 0x1f1e1d1c1b1a1918)
+ MISALIGNED_STORE_TEST(75, sd, ld, s0, 31, 0x2726252423222120)
+#endif
+
+# cacheline crossing
+ MISALIGNED_STORE_TEST(76, sh, lh, s0, 63, SEXT(0x3534, 16))
+ MISALIGNED_STORE_TEST(77, sh, lhu, s0, 63, 0x3736)
+ MISALIGNED_STORE_TEST(78, sw, lw, s0, 61, SEXT(0x3b3a3938, 32))
+ MISALIGNED_STORE_TEST(79, sw, lw, s0, 62, SEXT(0x3f3e3d3c, 32))
+ MISALIGNED_STORE_TEST(80, sw, lw, s0, 63, SEXT(0x43424140, 32))
+
+#if __riscv_xlen == 64
+ MISALIGNED_STORE_TEST(81, sw, lwu, s0, 61, 0x47464544)
+ MISALIGNED_STORE_TEST(82, sw, lwu, s0, 62, 0x4b4a4948)
+ MISALIGNED_STORE_TEST(83, sw, lwu, s0, 63, 0x4f4e4d4c)
+
+ MISALIGNED_STORE_TEST(84, sd, ld, s0, 57, 0x5756555453525150)
+ MISALIGNED_STORE_TEST(85, sd, ld, s0, 58, 0x5f5e5d5c5b5a5958)
+ MISALIGNED_STORE_TEST(86, sd, ld, s0, 59, 0x6766656463626160)
+ MISALIGNED_STORE_TEST(87, sd, ld, s0, 60, 0x6f6e6d6c6b6a6968)
+ MISALIGNED_STORE_TEST(88, sd, ld, s0, 61, 0x7776757473727170)
+ MISALIGNED_STORE_TEST(89, sd, ld, s0, 62, 0x7f7e7d7c7b7a7978)
+ MISALIGNED_STORE_TEST(90, sd, ld, s0, 63, 0x8786858483828180)
+#endif
+
+
+/* Check that a misaligned store writes the correct value, checked by a narrower load. */
+#define MISMATCHED_STORE_TEST(testnum, st_insn, ld_insn, base, st_offset, ld_offset, st_data, ld_data) \
+ li TESTNUM, testnum; \
+ li t1, st_data; \
+ li t2, ld_data; \
+ st_insn t1, st_offset(base); \
+ ld_insn t3, ld_offset(base); \
+ bne t2, t3, fail; \
+1:
+
+# within quadword
+ MISMATCHED_STORE_TEST(91, sh, lb, s0, 1, 1, 0x9998, SEXT(0x98, 8))
+ MISMATCHED_STORE_TEST(92, sh, lb, s0, 1, 2, 0x9b9a, SEXT(0x9b, 8))
+ MISMATCHED_STORE_TEST(93, sh, lbu, s0, 1, 1, 0x9d9c, 0x9c)
+ MISMATCHED_STORE_TEST(94, sh, lbu, s0, 1, 2, 0x9f9e, 0x9f)
+ MISMATCHED_STORE_TEST(95, sw, lb, s0, 1, 1, 0xa3a2a1a0, SEXT(0xa0, 8))
+ MISMATCHED_STORE_TEST(96, sw, lbu, s0, 2, 3, 0xa7a6a5a4, 0xa5)
+ MISMATCHED_STORE_TEST(97, sw, lh, s0, 3, 4, 0xabaaa9a8, SEXT(0xaaa9, 16))
+ MISMATCHED_STORE_TEST(98, sw, lhu, s0, 3, 5, 0xafaeadac, 0xafae)
+
+#if __riscv_xlen == 64
+ MISMATCHED_STORE_TEST(99, sd, lb, s0, 1, 7, 0xb7b6b5b4b3b2b1b0, SEXT(0xb6, 8))
+ MISMATCHED_STORE_TEST(100, sd, lbu, s0, 2, 3, 0xbfbebdbcbbbab9b8, 0xb9)
+ MISMATCHED_STORE_TEST(101, sd, lh, s0, 3, 9, 0xc7c6c5c4c3c2c1c0, SEXT(0xc7c6, 16))
+ MISMATCHED_STORE_TEST(102, sd, lhu, s0, 4, 5, 0xcfcecdcccbcac9c8, 0xcac9)
+ MISMATCHED_STORE_TEST(103, sd, lw, s0, 5, 9, 0xd7d6d5d4d3d2d1d0, SEXT(0xd7d6d5d4, 32))
+ MISMATCHED_STORE_TEST(104, sd, lw, s0, 6, 8, 0xdfdedddcdbdad9d8, SEXT(0xdddcdbda, 32))
+ MISMATCHED_STORE_TEST(105, sd, lwu, s0, 7, 8, 0xe7e6e5e4e3e2e1e0, 0xe4e3e2e1)
+#endif
+
+# octword crossing
+ MISMATCHED_STORE_TEST(106, sh, lb, s0, 31, 31, 0xe9e8, SEXT(0xe8, 8))
+ MISMATCHED_STORE_TEST(107, sh, lb, s0, 31, 32, 0xebea, SEXT(0xeb, 8))
+ MISMATCHED_STORE_TEST(108, sh, lbu, s0, 31, 31, 0xedec, 0xec)
+ MISMATCHED_STORE_TEST(109, sh, lbu, s0, 31, 32, 0xefee, 0xef)
+ MISMATCHED_STORE_TEST(110, sw, lb, s0, 29, 29, 0xf3f2f1f0, SEXT(0xf0, 8))
+ MISMATCHED_STORE_TEST(111, sw, lbu, s0, 30, 32, 0xf7f6f5f4, 0xf6)
+ MISMATCHED_STORE_TEST(112, sw, lh, s0, 29, 31, 0xfbfaf9f8, SEXT(0xfbfa, 16))
+ MISMATCHED_STORE_TEST(113, sw, lhu, s0, 31, 31, 0xfffefdfc, 0xfdfc)
+
+#if __riscv_xlen == 64
+ MISMATCHED_STORE_TEST(114, sd, lb, s0, 25, 32, 0x0706050403020100, SEXT(0x07, 8))
+ MISMATCHED_STORE_TEST(115, sd, lbu, s0, 26, 33, 0x0f0e0d0c0b0a0908, 0x0f)
+ MISMATCHED_STORE_TEST(116, sd, lh, s0, 27, 31, 0x1716151413121110, SEXT(0x1514, 16))
+ MISMATCHED_STORE_TEST(117, sd, lhu, s0, 28, 31, 0x1f1e1d1c1b1a1918, 0x1c1b)
+ MISMATCHED_STORE_TEST(118, sd, lw, s0, 29, 29, 0x2726252423222120, SEXT(0x23222120, 32))
+ MISMATCHED_STORE_TEST(119, sd, lw, s0, 30, 30, 0x2f2e2d2c2b2a2928, SEXT(0x2b2a2928, 32))
+ MISMATCHED_STORE_TEST(120, sd, lwu, s0, 31, 31, 0x3736353433323130, 0x33323130)
+#endif
+
+# cacheline crossing
+ MISMATCHED_STORE_TEST(121, sh, lb, s0, 63, 63, 0x4948, SEXT(0x48, 8))
+ MISMATCHED_STORE_TEST(122, sh, lb, s0, 63, 64, 0x4b4a, SEXT(0x4b, 8))
+ MISMATCHED_STORE_TEST(123, sh, lbu, s0, 63, 63, 0x4d4c, 0x4c)
+ MISMATCHED_STORE_TEST(124, sh, lbu, s0, 63, 64, 0x4f4e, 0x4f)
+ MISMATCHED_STORE_TEST(125, sw, lb, s0, 61, 61, 0x53525150, SEXT(0x50, 8))
+ MISMATCHED_STORE_TEST(126, sw, lbu, s0, 62, 64, 0x57565554, 0x56)
+ MISMATCHED_STORE_TEST(127, sw, lh, s0, 61, 63, 0x5b5a5958, SEXT(0x5b5a, 16))
+ MISMATCHED_STORE_TEST(128, sw, lhu, s0, 63, 63, 0x5f5e5d5c, 0x5d5c)
+
+#if __riscv_xlen == 64
+ MISMATCHED_STORE_TEST(129, sd, lb, s0, 57, 64, 0x6766656463626160, SEXT(0x67, 8))
+ MISMATCHED_STORE_TEST(130, sd, lbu, s0, 58, 65, 0x6f6e6d6c6b6a6968, 0x6f)
+ MISMATCHED_STORE_TEST(131, sd, lh, s0, 59, 63, 0x7776757473727170, SEXT(0x7574, 16))
+ MISMATCHED_STORE_TEST(132, sd, lhu, s0, 60, 63, 0x7f7e7d7c7b7a7978, 0x7c7b)
+ MISMATCHED_STORE_TEST(133, sd, lw, s0, 61, 61, 0x8786858483828180, SEXT(0x83828180, 32))
+ MISMATCHED_STORE_TEST(134, sd, lw, s0, 62, 62, 0x8f8e8d8c8b8a8988, SEXT(0x8b8a8988, 32))
+ MISMATCHED_STORE_TEST(135, sd, lwu, s0, 63, 63, 0x9796959493929190, 0x93929190)
+#endif
+
+/* Memory contents at this point should be:
+.word 0x10080000
+.word 0x30282018
+.word 0x34333231
+.word 0x0f373635
+.word 0x13121110
+.word 0x17161514
+.word 0x10080018
+.word 0x30282018
+
+.word 0x34333231
+.word 0x27373635
+.word 0x2b2a2928
+.word 0x2f2e2d2c
+.word 0x33323130
+.word 0x37363534
+.word 0x70686038
+.word 0x90888078
+
+.word 0x94939291
+.word 0x47979695
+.word 0x4b4a4948
+.word 0x4f4e4d4c
+.word 0x53525150
+.word 0x57565554
+.word 0x5b5a5958
+.word 0x5f5e5d5c
+.word 0x63626160
+.word 0x67666564
+.word 0x6b6a6968
+.word 0x6f6e6d6c
+.word 0x73727170
+.word 0x77767574
+.word 0x7b7a7978
+.word 0x7f7e7d7c
+*/
+
+/* Check that a misaligned store writes the correct value, checked by a wider load. */
+
+#if __riscv_xlen == 64
+# within quadword
+ MISMATCHED_STORE_TEST(136, sb, lh, s0, 1, 1, 0x98, SEXT(0xb898, 16))
+ MISMATCHED_STORE_TEST(137, sb, lhu, s0, 2, 1, 0x99, 0x9998)
+ MISMATCHED_STORE_TEST(138, sh, lw, s0, 1, 1, 0x9b9a, SEXT(0xc8c09b9a, 32))
+ MISMATCHED_STORE_TEST(139, sh, lw, s0, 3, 2, 0x9d9c, SEXT(0xd09d9c9b, 32))
+ MISMATCHED_STORE_TEST(140, sh, lw, s0, 5, 3, 0x9f9e, SEXT(0x9f9e9d9c, 32))
+
+ MISMATCHED_STORE_TEST(141, sb, lwu, s0, 2, 1, 0xa0, 0x9d9ca09a)
+ MISMATCHED_STORE_TEST(142, sh, lwu, s0, 3, 2, 0xa2a1, 0x9ea2a1a0)
+ MISMATCHED_STORE_TEST(143, sh, lwu, s0, 5, 3, 0xa4a3, 0xa4a3a2a1)
+
+ MISMATCHED_STORE_TEST(144, sb, ld, s0, 2, 1, 0xa5, 0xe1e0a4a3a2a1a59a)
+ MISMATCHED_STORE_TEST(145, sh, ld, s0, 7, 2, 0xa7a6, 0xe2a7a6a4a3a2a1a5)
+ MISMATCHED_STORE_TEST(146, sh, ld, s0, 9, 3, 0xa9a8, 0xa9a8a7a6a4a3a2a1)
+ MISMATCHED_STORE_TEST(147, sw, ld, s0, 5, 4, 0xadacabaa, 0xe4a9a8adacabaaa2)
+ MISMATCHED_STORE_TEST(148, sw, ld, s0, 7, 5, 0xb1b0afae, 0xe5e4b1b0afaeabaa)
+ MISMATCHED_STORE_TEST(149, sw, ld, s0, 9, 6, 0xb5b4b3b2, 0xe6b5b4b3b2afaeab)
+ MISMATCHED_STORE_TEST(150, sw, ld, s0, 11, 7, 0xb9b8b7b6, 0xb9b8b7b6b3b2afae)
+
+# octword crossing
+ MISMATCHED_STORE_TEST(151, sb, lh, s0, 31, 31, 0xba, SEXT(0x31ba, 16))
+ MISMATCHED_STORE_TEST(152, sb, lhu, s0, 32, 31, 0xbb, 0xbbba)
+ MISMATCHED_STORE_TEST(153, sh, lw, s0, 30, 30, 0xbdbc, SEXT(0x32bbbdbc, 32))
+ MISMATCHED_STORE_TEST(154, sh, lw, s0, 31, 30, 0xbfbe, SEXT(0x32bfbebc, 32))
+ MISMATCHED_STORE_TEST(155, sh, lw, s0, 32, 30, 0xc1c0, SEXT(0xc1c0bebc, 32))
+
+ MISMATCHED_STORE_TEST(156, sb, lwu, s0, 32, 31, 0xc2, 0x33c1c2be)
+ MISMATCHED_STORE_TEST(157, sh, lwu, s0, 31, 29, 0xc4c3, 0xc4c3bc20)
+ MISMATCHED_STORE_TEST(158, sh, lwu, s0, 32, 30, 0xc6c5, 0xc6c5c3bc)
+
+ MISMATCHED_STORE_TEST(159, sb, ld, s0, 32, 25, 0xc7, 0xc7c3bc2018100800)
+ MISMATCHED_STORE_TEST(160, sh, ld, s0, 31, 26, 0xc9c8, 0xc6c9c8bc20181008)
+ MISMATCHED_STORE_TEST(161, sh, ld, s0, 31, 27, 0xcbca, 0x33c6cbcabc201810)
+ MISMATCHED_STORE_TEST(162, sw, ld, s0, 32, 28, 0xcfcecdcc, 0xcfcecdcccabc2018)
+ MISMATCHED_STORE_TEST(163, sw, ld, s0, 31, 29, 0xd3d2d1d0, 0x35cfd3d2d1d0bc20)
+ MISMATCHED_STORE_TEST(164, sw, ld, s0, 30, 30, 0xd7d6d5d4, 0x3635cfd3d7d6d5d4)
+ MISMATCHED_STORE_TEST(165, sw, ld, s0, 29, 31, 0xdbdad9d8, 0x373635cfd3d7dbda)
+
+# cacheline crossing
+ MISMATCHED_STORE_TEST(166, sb, lh, s0, 63, 63, 0xdc, SEXT(0x91dc, 16))
+ MISMATCHED_STORE_TEST(167, sb, lhu, s0, 64, 63, 0xdd, 0xdddc)
+ MISMATCHED_STORE_TEST(168, sh, lw, s0, 62, 62, 0xdfde, SEXT(0x92dddfde, 32))
+ MISMATCHED_STORE_TEST(169, sh, lw, s0, 63, 62, 0xe1e0, SEXT(0x92e1e0de, 32))
+ MISMATCHED_STORE_TEST(170, sh, lw, s0, 64, 62, 0xe3e2, SEXT(0xe3e2e0de, 32))
+
+ MISMATCHED_STORE_TEST(171, sb, lwu, s0, 64, 63, 0xe4, 0x93e3e4e0)
+ MISMATCHED_STORE_TEST(172, sh, lwu, s0, 63, 61, 0xe6e5, 0xe6e5de80)
+ MISMATCHED_STORE_TEST(173, sh, lwu, s0, 64, 62, 0xe8e7, 0xe8e7e5de)
+
+ MISMATCHED_STORE_TEST(174, sb, ld, s0, 64, 57, 0xe9, 0xe9e5de8078706860)
+ MISMATCHED_STORE_TEST(175, sh, ld, s0, 63, 58, 0xebea, 0xe8ebeade80787068)
+ MISMATCHED_STORE_TEST(176, sh, ld, s0, 63, 59, 0xedec, 0x93e8edecde807870)
+ MISMATCHED_STORE_TEST(177, sw, ld, s0, 64, 60, 0xf1f0efee, 0xf1f0efeeecde8078)
+ MISMATCHED_STORE_TEST(178, sw, ld, s0, 63, 61, 0xf5f4f3f2, 0x95f1f5f4f3f2de80)
+ MISMATCHED_STORE_TEST(179, sw, ld, s0, 62, 62, 0xf9f8f7f6, 0x9695f1f5f9f8f7f6)
+ MISMATCHED_STORE_TEST(180, sw, ld, s0, 61, 63, 0xfdfcfbfa, 0x979695f1f5f9fdfc)
+#endif
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+data:
+ .align 3
+
+.word 0x03020100
+.word 0x07060504
+.word 0x0b0a0908
+.word 0x0f0e0d0c
+.word 0x13121110
+.word 0x17161514
+.word 0x1b1a1918
+.word 0x1f1e1d1c
+.word 0x23222120
+.word 0x27262524
+.word 0x2b2a2928
+.word 0x2f2e2d2c
+.word 0x33323130
+.word 0x37363534
+.word 0x3b3a3938
+.word 0x3f3e3d3c
+
+.word 0x43424140
+.word 0x47464544
+.word 0x4b4a4948
+.word 0x4f4e4d4c
+.word 0x53525150
+.word 0x57565554
+.word 0x5b5a5958
+.word 0x5f5e5d5c
+.word 0x63626160
+.word 0x67666564
+.word 0x6b6a6968
+.word 0x6f6e6d6c
+.word 0x73727170
+.word 0x77767574
+.word 0x7b7a7978
+.word 0x7f7e7d7c
+
+.fill 0xff, 1, 80
+
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/or.S b/tests/riscv-tests/rv32ui/or.S
@@ -0,0 +1,69 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# or.S
+#-----------------------------------------------------------------------------
+#
+# Test or instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Logical tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_OP( 3, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
+ TEST_RR_OP( 4, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
+ TEST_RR_OP( 5, or, 0xf0fff0ff, 0xf00ff00f, 0xf0f0f0f0 );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 6, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_SRC2_EQ_DEST( 7, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_SRC12_EQ_DEST( 8, or, 0xff00ff00, 0xff00ff00 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 9, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_DEST_BYPASS( 10, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
+ TEST_RR_DEST_BYPASS( 11, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
+
+ TEST_RR_SRC12_BYPASS( 12, 0, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_SRC12_BYPASS( 13, 0, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
+ TEST_RR_SRC12_BYPASS( 14, 0, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
+ TEST_RR_SRC12_BYPASS( 15, 1, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_SRC12_BYPASS( 16, 1, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
+ TEST_RR_SRC12_BYPASS( 17, 2, 0, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
+
+ TEST_RR_SRC21_BYPASS( 18, 0, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_SRC21_BYPASS( 19, 0, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
+ TEST_RR_SRC21_BYPASS( 20, 0, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
+ TEST_RR_SRC21_BYPASS( 21, 1, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_SRC21_BYPASS( 22, 1, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
+ TEST_RR_SRC21_BYPASS( 23, 2, 0, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
+
+ TEST_RR_ZEROSRC1( 24, or, 0xff00ff00, 0xff00ff00 );
+ TEST_RR_ZEROSRC2( 25, or, 0x00ff00ff, 0x00ff00ff );
+ TEST_RR_ZEROSRC12( 26, or, 0 );
+ TEST_RR_ZERODEST( 27, or, 0x11111111, 0x22222222 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/ori.S b/tests/riscv-tests/rv32ui/ori.S
@@ -0,0 +1,55 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# ori.S
+#-----------------------------------------------------------------------------
+#
+# Test ori instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Logical tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_OP( 2, ori, 0xffffffffffffff0f, 0xffffffffff00ff00, 0xf0f );
+ TEST_IMM_OP( 3, ori, 0x000000000ff00ff0, 0x000000000ff00ff0, 0x0f0 );
+ TEST_IMM_OP( 4, ori, 0x0000000000ff07ff, 0x0000000000ff00ff, 0x70f );
+ TEST_IMM_OP( 5, ori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_SRC1_EQ_DEST( 6, ori, 0xff00fff0, 0xff00ff00, 0x0f0 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_DEST_BYPASS( 7, 0, ori, 0x000000000ff00ff0, 0x000000000ff00ff0, 0x0f0 );
+ TEST_IMM_DEST_BYPASS( 8, 1, ori, 0x0000000000ff07ff, 0x0000000000ff00ff, 0x70f );
+ TEST_IMM_DEST_BYPASS( 9, 2, ori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 );
+
+ TEST_IMM_SRC1_BYPASS( 10, 0, ori, 0x000000000ff00ff0, 0x000000000ff00ff0, 0x0f0 );
+ TEST_IMM_SRC1_BYPASS( 11, 1, ori, 0xffffffffffffffff, 0x0000000000ff00ff, 0xf0f );
+ TEST_IMM_SRC1_BYPASS( 12, 2, ori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 );
+
+ TEST_IMM_ZEROSRC1( 13, ori, 0x0f0, 0x0f0 );
+ TEST_IMM_ZERODEST( 14, ori, 0x00ff00ff, 0x70f );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/sb.S b/tests/riscv-tests/rv32ui/sb.S
@@ -0,0 +1,96 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sb.S
+#-----------------------------------------------------------------------------
+#
+# Test sb instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Basic tests
+ #-------------------------------------------------------------
+
+ TEST_ST_OP( 2, lb, sb, 0xffffffffffffffaa, 0, tdat );
+ TEST_ST_OP( 3, lb, sb, 0x0000000000000000, 1, tdat );
+ TEST_ST_OP( 4, lh, sb, 0xffffffffffffefa0, 2, tdat );
+ TEST_ST_OP( 5, lb, sb, 0x000000000000000a, 3, tdat );
+
+ # Test with negative offset
+
+ TEST_ST_OP( 6, lb, sb, 0xffffffffffffffaa, -3, tdat8 );
+ TEST_ST_OP( 7, lb, sb, 0x0000000000000000, -2, tdat8 );
+ TEST_ST_OP( 8, lb, sb, 0xffffffffffffffa0, -1, tdat8 );
+ TEST_ST_OP( 9, lb, sb, 0x000000000000000a, 0, tdat8 );
+
+ # Test with a negative base
+
+ TEST_CASE( 10, x5, 0x78, \
+ la x1, tdat9; \
+ li x2, 0x12345678; \
+ addi x4, x1, -32; \
+ sb x2, 32(x4); \
+ lb x5, 0(x1); \
+ )
+
+ # Test with unaligned base
+
+ TEST_CASE( 11, x5, 0xffffffffffffff98, \
+ la x1, tdat9; \
+ li x2, 0x00003098; \
+ addi x1, x1, -6; \
+ sb x2, 7(x1); \
+ la x4, tdat10; \
+ lb x5, 0(x4); \
+ )
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_ST_SRC12_BYPASS( 12, 0, 0, lb, sb, 0xffffffffffffffdd, 0, tdat );
+ TEST_ST_SRC12_BYPASS( 13, 0, 1, lb, sb, 0xffffffffffffffcd, 1, tdat );
+ TEST_ST_SRC12_BYPASS( 14, 0, 2, lb, sb, 0xffffffffffffffcc, 2, tdat );
+ TEST_ST_SRC12_BYPASS( 15, 1, 0, lb, sb, 0xffffffffffffffbc, 3, tdat );
+ TEST_ST_SRC12_BYPASS( 16, 1, 1, lb, sb, 0xffffffffffffffbb, 4, tdat );
+ TEST_ST_SRC12_BYPASS( 17, 2, 0, lb, sb, 0xffffffffffffffab, 5, tdat );
+
+ TEST_ST_SRC21_BYPASS( 18, 0, 0, lb, sb, 0x33, 0, tdat );
+ TEST_ST_SRC21_BYPASS( 19, 0, 1, lb, sb, 0x23, 1, tdat );
+ TEST_ST_SRC21_BYPASS( 20, 0, 2, lb, sb, 0x22, 2, tdat );
+ TEST_ST_SRC21_BYPASS( 21, 1, 0, lb, sb, 0x12, 3, tdat );
+ TEST_ST_SRC21_BYPASS( 22, 1, 1, lb, sb, 0x11, 4, tdat );
+ TEST_ST_SRC21_BYPASS( 23, 2, 0, lb, sb, 0x01, 5, tdat );
+
+ li a0, 0xef
+ la a1, tdat
+ sb a0, 3(a1)
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+tdat:
+tdat1: .byte 0xef
+tdat2: .byte 0xef
+tdat3: .byte 0xef
+tdat4: .byte 0xef
+tdat5: .byte 0xef
+tdat6: .byte 0xef
+tdat7: .byte 0xef
+tdat8: .byte 0xef
+tdat9: .byte 0xef
+tdat10: .byte 0xef
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/sd.S b/tests/riscv-tests/rv32ui/sd.S
@@ -0,0 +1,92 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sd.S
+#-----------------------------------------------------------------------------
+#
+# Test sd instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Basic tests
+ #-------------------------------------------------------------
+
+ TEST_ST_OP( 2, ld, sd, 0x00aa00aa00aa00aa, 0, tdat );
+ TEST_ST_OP( 3, ld, sd, 0xaa00aa00aa00aa00, 8, tdat );
+ TEST_ST_OP( 4, ld, sd, 0x0aa00aa00aa00aa0, 16, tdat );
+ TEST_ST_OP( 5, ld, sd, 0xa00aa00aa00aa00a, 24, tdat );
+
+ # Test with negative offset
+
+ TEST_ST_OP( 6, ld, sd, 0x00aa00aa00aa00aa, -24, tdat8 );
+ TEST_ST_OP( 7, ld, sd, 0xaa00aa00aa00aa00, -16, tdat8 );
+ TEST_ST_OP( 8, ld, sd, 0x0aa00aa00aa00aa0, -8, tdat8 );
+ TEST_ST_OP( 9, ld, sd, 0xa00aa00aa00aa00a, 0, tdat8 );
+
+ # Test with a negative base
+
+ TEST_CASE( 10, x5, 0x1234567812345678, \
+ la x1, tdat9; \
+ li x2, 0x1234567812345678; \
+ addi x4, x1, -32; \
+ sd x2, 32(x4); \
+ ld x5, 0(x1); \
+ )
+
+ # Test with unaligned base
+
+ TEST_CASE( 11, x5, 0x5821309858213098, \
+ la x1, tdat9; \
+ li x2, 0x5821309858213098; \
+ addi x1, x1, -3; \
+ sd x2, 11(x1); \
+ la x4, tdat10; \
+ ld x5, 0(x4); \
+ )
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_ST_SRC12_BYPASS( 12, 0, 0, ld, sd, 0xabbccdd, 0, tdat );
+ TEST_ST_SRC12_BYPASS( 13, 0, 1, ld, sd, 0xaabbccd, 8, tdat );
+ TEST_ST_SRC12_BYPASS( 14, 0, 2, ld, sd, 0xdaabbcc, 16, tdat );
+ TEST_ST_SRC12_BYPASS( 15, 1, 0, ld, sd, 0xddaabbc, 24, tdat );
+ TEST_ST_SRC12_BYPASS( 16, 1, 1, ld, sd, 0xcddaabb, 32, tdat );
+ TEST_ST_SRC12_BYPASS( 17, 2, 0, ld, sd, 0xccddaab, 40, tdat );
+
+ TEST_ST_SRC21_BYPASS( 18, 0, 0, ld, sd, 0x00112233, 0, tdat );
+ TEST_ST_SRC21_BYPASS( 19, 0, 1, ld, sd, 0x30011223, 8, tdat );
+ TEST_ST_SRC21_BYPASS( 20, 0, 2, ld, sd, 0x33001122, 16, tdat );
+ TEST_ST_SRC21_BYPASS( 21, 1, 0, ld, sd, 0x23300112, 24, tdat );
+ TEST_ST_SRC21_BYPASS( 22, 1, 1, ld, sd, 0x22330011, 32, tdat );
+ TEST_ST_SRC21_BYPASS( 23, 2, 0, ld, sd, 0x12233001, 40, tdat );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+tdat:
+tdat1: .dword 0xdeadbeefdeadbeef
+tdat2: .dword 0xdeadbeefdeadbeef
+tdat3: .dword 0xdeadbeefdeadbeef
+tdat4: .dword 0xdeadbeefdeadbeef
+tdat5: .dword 0xdeadbeefdeadbeef
+tdat6: .dword 0xdeadbeefdeadbeef
+tdat7: .dword 0xdeadbeefdeadbeef
+tdat8: .dword 0xdeadbeefdeadbeef
+tdat9: .dword 0xdeadbeefdeadbeef
+tdat10: .dword 0xdeadbeefdeadbeef
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/sh.S b/tests/riscv-tests/rv32ui/sh.S
@@ -0,0 +1,96 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sh.S
+#-----------------------------------------------------------------------------
+#
+# Test sh instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Basic tests
+ #-------------------------------------------------------------
+
+ TEST_ST_OP( 2, lh, sh, 0x00000000000000aa, 0, tdat );
+ TEST_ST_OP( 3, lh, sh, 0xffffffffffffaa00, 2, tdat );
+ TEST_ST_OP( 4, lw, sh, 0xffffffffbeef0aa0, 4, tdat );
+ TEST_ST_OP( 5, lh, sh, 0xffffffffffffa00a, 6, tdat );
+
+ # Test with negative offset
+
+ TEST_ST_OP( 6, lh, sh, 0x00000000000000aa, -6, tdat8 );
+ TEST_ST_OP( 7, lh, sh, 0xffffffffffffaa00, -4, tdat8 );
+ TEST_ST_OP( 8, lh, sh, 0x0000000000000aa0, -2, tdat8 );
+ TEST_ST_OP( 9, lh, sh, 0xffffffffffffa00a, 0, tdat8 );
+
+ # Test with a negative base
+
+ TEST_CASE( 10, x5, 0x5678, \
+ la x1, tdat9; \
+ li x2, 0x12345678; \
+ addi x4, x1, -32; \
+ sh x2, 32(x4); \
+ lh x5, 0(x1); \
+ )
+
+ # Test with unaligned base
+
+ TEST_CASE( 11, x5, 0x3098, \
+ la x1, tdat9; \
+ li x2, 0x00003098; \
+ addi x1, x1, -5; \
+ sh x2, 7(x1); \
+ la x4, tdat10; \
+ lh x5, 0(x4); \
+ )
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_ST_SRC12_BYPASS( 12, 0, 0, lh, sh, 0xffffffffffffccdd, 0, tdat );
+ TEST_ST_SRC12_BYPASS( 13, 0, 1, lh, sh, 0xffffffffffffbccd, 2, tdat );
+ TEST_ST_SRC12_BYPASS( 14, 0, 2, lh, sh, 0xffffffffffffbbcc, 4, tdat );
+ TEST_ST_SRC12_BYPASS( 15, 1, 0, lh, sh, 0xffffffffffffabbc, 6, tdat );
+ TEST_ST_SRC12_BYPASS( 16, 1, 1, lh, sh, 0xffffffffffffaabb, 8, tdat );
+ TEST_ST_SRC12_BYPASS( 17, 2, 0, lh, sh, 0xffffffffffffdaab, 10, tdat );
+
+ TEST_ST_SRC21_BYPASS( 18, 0, 0, lh, sh, 0x2233, 0, tdat );
+ TEST_ST_SRC21_BYPASS( 19, 0, 1, lh, sh, 0x1223, 2, tdat );
+ TEST_ST_SRC21_BYPASS( 20, 0, 2, lh, sh, 0x1122, 4, tdat );
+ TEST_ST_SRC21_BYPASS( 21, 1, 0, lh, sh, 0x0112, 6, tdat );
+ TEST_ST_SRC21_BYPASS( 22, 1, 1, lh, sh, 0x0011, 8, tdat );
+ TEST_ST_SRC21_BYPASS( 23, 2, 0, lh, sh, 0x3001, 10, tdat );
+
+ li a0, 0xbeef
+ la a1, tdat
+ sh a0, 6(a1)
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+tdat:
+tdat1: .half 0xbeef
+tdat2: .half 0xbeef
+tdat3: .half 0xbeef
+tdat4: .half 0xbeef
+tdat5: .half 0xbeef
+tdat6: .half 0xbeef
+tdat7: .half 0xbeef
+tdat8: .half 0xbeef
+tdat9: .half 0xbeef
+tdat10: .half 0xbeef
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/simple.S b/tests/riscv-tests/rv32ui/simple.S
@@ -0,0 +1,27 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# simple.S
+#-----------------------------------------------------------------------------
+#
+# This is the most basic self checking test. If your simulator does not
+# pass thiss then there is little chance that it will pass any of the
+# more complicated self checking tests.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+RVTEST_PASS
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/sll.S b/tests/riscv-tests/rv32ui/sll.S
@@ -0,0 +1,96 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sll.S
+#-----------------------------------------------------------------------------
+#
+# Test sll instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, sll, 0x0000000000000001, 0x0000000000000001, 0 );
+ TEST_RR_OP( 3, sll, 0x0000000000000002, 0x0000000000000001, 1 );
+ TEST_RR_OP( 4, sll, 0x0000000000000080, 0x0000000000000001, 7 );
+ TEST_RR_OP( 5, sll, 0x0000000000004000, 0x0000000000000001, 14 );
+ TEST_RR_OP( 6, sll, 0x0000000080000000, 0x0000000000000001, 31 );
+
+ TEST_RR_OP( 7, sll, 0xffffffffffffffff, 0xffffffffffffffff, 0 );
+ TEST_RR_OP( 8, sll, 0xfffffffffffffffe, 0xffffffffffffffff, 1 );
+ TEST_RR_OP( 9, sll, 0xffffffffffffff80, 0xffffffffffffffff, 7 );
+ TEST_RR_OP( 10, sll, 0xffffffffffffc000, 0xffffffffffffffff, 14 );
+ TEST_RR_OP( 11, sll, 0xffffffff80000000, 0xffffffffffffffff, 31 );
+
+ TEST_RR_OP( 12, sll, 0x0000000021212121, 0x0000000021212121, 0 );
+ TEST_RR_OP( 13, sll, 0x0000000042424242, 0x0000000021212121, 1 );
+ TEST_RR_OP( 14, sll, 0x0000001090909080, 0x0000000021212121, 7 );
+ TEST_RR_OP( 15, sll, 0x0000084848484000, 0x0000000021212121, 14 );
+ TEST_RR_OP( 16, sll, 0x1090909080000000, 0x0000000021212121, 31 );
+
+ # Verify that shifts only use bottom six(rv64) or five(rv32) bits
+
+ TEST_RR_OP( 17, sll, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 );
+ TEST_RR_OP( 18, sll, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffc1 );
+ TEST_RR_OP( 19, sll, 0x0000001090909080, 0x0000000021212121, 0xffffffffffffffc7 );
+ TEST_RR_OP( 20, sll, 0x0000084848484000, 0x0000000021212121, 0xffffffffffffffce );
+
+#if __riscv_xlen == 64
+ TEST_RR_OP( 21, sll, 0x8000000000000000, 0x0000000021212121, 0xffffffffffffffff );
+ TEST_RR_OP( 50, sll, 0x8000000000000000, 0x0000000000000001, 63 );
+ TEST_RR_OP( 51, sll, 0xffffff8000000000, 0xffffffffffffffff, 39 );
+ TEST_RR_OP( 52, sll, 0x0909080000000000, 0x0000000021212121, 43 );
+#endif
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 22, sll, 0x00000080, 0x00000001, 7 );
+ TEST_RR_SRC2_EQ_DEST( 23, sll, 0x00004000, 0x00000001, 14 );
+ TEST_RR_SRC12_EQ_DEST( 24, sll, 24, 3 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 25, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 );
+ TEST_RR_DEST_BYPASS( 26, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 );
+ TEST_RR_DEST_BYPASS( 27, 2, sll, 0x0000000080000000, 0x0000000000000001, 31 );
+
+ TEST_RR_SRC12_BYPASS( 28, 0, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 );
+ TEST_RR_SRC12_BYPASS( 29, 0, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 );
+ TEST_RR_SRC12_BYPASS( 30, 0, 2, sll, 0x0000000080000000, 0x0000000000000001, 31 );
+ TEST_RR_SRC12_BYPASS( 31, 1, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 );
+ TEST_RR_SRC12_BYPASS( 32, 1, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 );
+ TEST_RR_SRC12_BYPASS( 33, 2, 0, sll, 0x0000000080000000, 0x0000000000000001, 31 );
+
+ TEST_RR_SRC21_BYPASS( 34, 0, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 );
+ TEST_RR_SRC21_BYPASS( 35, 0, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 );
+ TEST_RR_SRC21_BYPASS( 36, 0, 2, sll, 0x0000000080000000, 0x0000000000000001, 31 );
+ TEST_RR_SRC21_BYPASS( 37, 1, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 );
+ TEST_RR_SRC21_BYPASS( 38, 1, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 );
+ TEST_RR_SRC21_BYPASS( 39, 2, 0, sll, 0x0000000080000000, 0x0000000000000001, 31 );
+
+ TEST_RR_ZEROSRC1( 40, sll, 0, 15 );
+ TEST_RR_ZEROSRC2( 41, sll, 32, 32 );
+ TEST_RR_ZEROSRC12( 42, sll, 0 );
+ TEST_RR_ZERODEST( 43, sll, 1024, 2048 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/slli.S b/tests/riscv-tests/rv32ui/slli.S
@@ -0,0 +1,74 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# slli.S
+#-----------------------------------------------------------------------------
+#
+# Test slli instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_OP( 2, slli, 0x0000000000000001, 0x0000000000000001, 0 );
+ TEST_IMM_OP( 3, slli, 0x0000000000000002, 0x0000000000000001, 1 );
+ TEST_IMM_OP( 4, slli, 0x0000000000000080, 0x0000000000000001, 7 );
+ TEST_IMM_OP( 5, slli, 0x0000000000004000, 0x0000000000000001, 14 );
+ TEST_IMM_OP( 6, slli, 0x0000000080000000, 0x0000000000000001, 31 );
+
+ TEST_IMM_OP( 7, slli, 0xffffffffffffffff, 0xffffffffffffffff, 0 );
+ TEST_IMM_OP( 8, slli, 0xfffffffffffffffe, 0xffffffffffffffff, 1 );
+ TEST_IMM_OP( 9, slli, 0xffffffffffffff80, 0xffffffffffffffff, 7 );
+ TEST_IMM_OP( 10, slli, 0xffffffffffffc000, 0xffffffffffffffff, 14 );
+ TEST_IMM_OP( 11, slli, 0xffffffff80000000, 0xffffffffffffffff, 31 );
+
+ TEST_IMM_OP( 12, slli, 0x0000000021212121, 0x0000000021212121, 0 );
+ TEST_IMM_OP( 13, slli, 0x0000000042424242, 0x0000000021212121, 1 );
+ TEST_IMM_OP( 14, slli, 0x0000001090909080, 0x0000000021212121, 7 );
+ TEST_IMM_OP( 15, slli, 0x0000084848484000, 0x0000000021212121, 14 );
+ TEST_IMM_OP( 16, slli, 0x1090909080000000, 0x0000000021212121, 31 );
+
+#if __riscv_xlen == 64
+ TEST_IMM_OP( 50, slli, 0x8000000000000000, 0x0000000000000001, 63 );
+ TEST_IMM_OP( 51, slli, 0xffffff8000000000, 0xffffffffffffffff, 39 );
+ TEST_IMM_OP( 52, slli, 0x0909080000000000, 0x0000000021212121, 43 );
+#endif
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_SRC1_EQ_DEST( 17, slli, 0x00000080, 0x00000001, 7 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_DEST_BYPASS( 18, 0, slli, 0x0000000000000080, 0x0000000000000001, 7 );
+ TEST_IMM_DEST_BYPASS( 19, 1, slli, 0x0000000000004000, 0x0000000000000001, 14 );
+ TEST_IMM_DEST_BYPASS( 20, 2, slli, 0x0000000080000000, 0x0000000000000001, 31 );
+
+ TEST_IMM_SRC1_BYPASS( 21, 0, slli, 0x0000000000000080, 0x0000000000000001, 7 );
+ TEST_IMM_SRC1_BYPASS( 22, 1, slli, 0x0000000000004000, 0x0000000000000001, 14 );
+ TEST_IMM_SRC1_BYPASS( 23, 2, slli, 0x0000000080000000, 0x0000000000000001, 31 );
+
+ TEST_IMM_ZEROSRC1( 24, slli, 0, 31 );
+ TEST_IMM_ZERODEST( 25, slli, 33, 20 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/slliw.S b/tests/riscv-tests/rv32ui/slliw.S
@@ -0,0 +1,75 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# slliw.S
+#-----------------------------------------------------------------------------
+#
+# Test slliw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_OP( 2, slliw, 0x0000000000000001, 0x0000000000000001, 0 );
+ TEST_IMM_OP( 3, slliw, 0x0000000000000002, 0x0000000000000001, 1 );
+ TEST_IMM_OP( 4, slliw, 0x0000000000000080, 0x0000000000000001, 7 );
+ TEST_IMM_OP( 5, slliw, 0x0000000000004000, 0x0000000000000001, 14 );
+ TEST_IMM_OP( 6, slliw, 0xffffffff80000000, 0x0000000000000001, 31 );
+
+ TEST_IMM_OP( 7, slliw, 0xffffffffffffffff, 0xffffffffffffffff, 0 );
+ TEST_IMM_OP( 8, slliw, 0xfffffffffffffffe, 0xffffffffffffffff, 1 );
+ TEST_IMM_OP( 9, slliw, 0xffffffffffffff80, 0xffffffffffffffff, 7 );
+ TEST_IMM_OP( 10, slliw, 0xffffffffffffc000, 0xffffffffffffffff, 14 );
+ TEST_IMM_OP( 11, slliw, 0xffffffff80000000, 0xffffffffffffffff, 31 );
+
+ TEST_IMM_OP( 12, slliw, 0x0000000021212121, 0x0000000021212121, 0 );
+ TEST_IMM_OP( 13, slliw, 0x0000000042424242, 0x0000000021212121, 1 );
+ TEST_IMM_OP( 14, slliw, 0xffffffff90909080, 0x0000000021212121, 7 );
+ TEST_IMM_OP( 15, slliw, 0x0000000048484000, 0x0000000021212121, 14 );
+ TEST_IMM_OP( 16, slliw, 0xffffffff80000000, 0x0000000021212121, 31 );
+
+ # Verify that shifts ignore top 32 (using true 64-bit values)
+
+ TEST_IMM_OP( 44, slliw, 0x0000000012345678, 0xffffffff12345678, 0 );
+ TEST_IMM_OP( 45, slliw, 0x0000000023456780, 0xffffffff12345678, 4 );
+ TEST_IMM_OP( 46, slliw, 0xffffffff92345678, 0x0000000092345678, 0 );
+ TEST_IMM_OP( 47, slliw, 0xffffffff93456780, 0x0000000099345678, 4 );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_SRC1_EQ_DEST( 17, slliw, 0x00000080, 0x00000001, 7 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_DEST_BYPASS( 18, 0, slliw, 0x0000000000000080, 0x0000000000000001, 7 );
+ TEST_IMM_DEST_BYPASS( 19, 1, slliw, 0x0000000000004000, 0x0000000000000001, 14 );
+ TEST_IMM_DEST_BYPASS( 20, 2, slliw, 0xffffffff80000000, 0x0000000000000001, 31 );
+
+ TEST_IMM_SRC1_BYPASS( 21, 0, slliw, 0x0000000000000080, 0x0000000000000001, 7 );
+ TEST_IMM_SRC1_BYPASS( 22, 1, slliw, 0x0000000000004000, 0x0000000000000001, 14 );
+ TEST_IMM_SRC1_BYPASS( 23, 2, slliw, 0xffffffff80000000, 0x0000000000000001, 31 );
+
+ TEST_IMM_ZEROSRC1( 24, slliw, 0, 31 );
+ TEST_IMM_ZERODEST( 25, slliw, 31, 28 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/sllw.S b/tests/riscv-tests/rv32ui/sllw.S
@@ -0,0 +1,97 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sllw.S
+#-----------------------------------------------------------------------------
+#
+# Test sllw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, sllw, 0x0000000000000001, 0x0000000000000001, 0 );
+ TEST_RR_OP( 3, sllw, 0x0000000000000002, 0x0000000000000001, 1 );
+ TEST_RR_OP( 4, sllw, 0x0000000000000080, 0x0000000000000001, 7 );
+ TEST_RR_OP( 5, sllw, 0x0000000000004000, 0x0000000000000001, 14 );
+ TEST_RR_OP( 6, sllw, 0xffffffff80000000, 0x0000000000000001, 31 );
+
+ TEST_RR_OP( 7, sllw, 0xffffffffffffffff, 0xffffffffffffffff, 0 );
+ TEST_RR_OP( 8, sllw, 0xfffffffffffffffe, 0xffffffffffffffff, 1 );
+ TEST_RR_OP( 9, sllw, 0xffffffffffffff80, 0xffffffffffffffff, 7 );
+ TEST_RR_OP( 10, sllw, 0xffffffffffffc000, 0xffffffffffffffff, 14 );
+ TEST_RR_OP( 11, sllw, 0xffffffff80000000, 0xffffffffffffffff, 31 );
+
+ TEST_RR_OP( 12, sllw, 0x0000000021212121, 0x0000000021212121, 0 );
+ TEST_RR_OP( 13, sllw, 0x0000000042424242, 0x0000000021212121, 1 );
+ TEST_RR_OP( 14, sllw, 0xffffffff90909080, 0x0000000021212121, 7 );
+ TEST_RR_OP( 15, sllw, 0x0000000048484000, 0x0000000021212121, 14 );
+ TEST_RR_OP( 16, sllw, 0xffffffff80000000, 0x0000000021212121, 31 );
+
+ # Verify that shifts only use bottom five bits
+
+ TEST_RR_OP( 17, sllw, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffe0 );
+ TEST_RR_OP( 18, sllw, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffe1 );
+ TEST_RR_OP( 19, sllw, 0xffffffff90909080, 0x0000000021212121, 0xffffffffffffffe7 );
+ TEST_RR_OP( 20, sllw, 0x0000000048484000, 0x0000000021212121, 0xffffffffffffffee );
+ TEST_RR_OP( 21, sllw, 0xffffffff80000000, 0x0000000021212121, 0xffffffffffffffff );
+
+ # Verify that shifts ignore top 32 (using true 64-bit values)
+
+ TEST_RR_OP( 44, sllw, 0x0000000012345678, 0xffffffff12345678, 0 );
+ TEST_RR_OP( 45, sllw, 0x0000000023456780, 0xffffffff12345678, 4 );
+ TEST_RR_OP( 46, sllw, 0xffffffff92345678, 0x0000000092345678, 0 );
+ TEST_RR_OP( 47, sllw, 0xffffffff93456780, 0x0000000099345678, 4 );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 22, sllw, 0x00000080, 0x00000001, 7 );
+ TEST_RR_SRC2_EQ_DEST( 23, sllw, 0x00004000, 0x00000001, 14 );
+ TEST_RR_SRC12_EQ_DEST( 24, sllw, 24, 3 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 25, 0, sllw, 0x0000000000000080, 0x0000000000000001, 7 );
+ TEST_RR_DEST_BYPASS( 26, 1, sllw, 0x0000000000004000, 0x0000000000000001, 14 );
+ TEST_RR_DEST_BYPASS( 27, 2, sllw, 0xffffffff80000000, 0x0000000000000001, 31 );
+
+ TEST_RR_SRC12_BYPASS( 28, 0, 0, sllw, 0x0000000000000080, 0x0000000000000001, 7 );
+ TEST_RR_SRC12_BYPASS( 29, 0, 1, sllw, 0x0000000000004000, 0x0000000000000001, 14 );
+ TEST_RR_SRC12_BYPASS( 30, 0, 2, sllw, 0xffffffff80000000, 0x0000000000000001, 31 );
+ TEST_RR_SRC12_BYPASS( 31, 1, 0, sllw, 0x0000000000000080, 0x0000000000000001, 7 );
+ TEST_RR_SRC12_BYPASS( 32, 1, 1, sllw, 0x0000000000004000, 0x0000000000000001, 14 );
+ TEST_RR_SRC12_BYPASS( 33, 2, 0, sllw, 0xffffffff80000000, 0x0000000000000001, 31 );
+
+ TEST_RR_SRC21_BYPASS( 34, 0, 0, sllw, 0x0000000000000080, 0x0000000000000001, 7 );
+ TEST_RR_SRC21_BYPASS( 35, 0, 1, sllw, 0x0000000000004000, 0x0000000000000001, 14 );
+ TEST_RR_SRC21_BYPASS( 36, 0, 2, sllw, 0xffffffff80000000, 0x0000000000000001, 31 );
+ TEST_RR_SRC21_BYPASS( 37, 1, 0, sllw, 0x0000000000000080, 0x0000000000000001, 7 );
+ TEST_RR_SRC21_BYPASS( 38, 1, 1, sllw, 0x0000000000004000, 0x0000000000000001, 14 );
+ TEST_RR_SRC21_BYPASS( 39, 2, 0, sllw, 0xffffffff80000000, 0x0000000000000001, 31 );
+
+ TEST_RR_ZEROSRC1( 40, sllw, 0, 15 );
+ TEST_RR_ZEROSRC2( 41, sllw, 32, 32 );
+ TEST_RR_ZEROSRC12( 42, sllw, 0 );
+ TEST_RR_ZERODEST( 43, sllw, 1024, 2048 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/slt.S b/tests/riscv-tests/rv32ui/slt.S
@@ -0,0 +1,84 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# slt.S
+#-----------------------------------------------------------------------------
+#
+# Test slt instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, slt, 0, 0x0000000000000000, 0x0000000000000000 );
+ TEST_RR_OP( 3, slt, 0, 0x0000000000000001, 0x0000000000000001 );
+ TEST_RR_OP( 4, slt, 1, 0x0000000000000003, 0x0000000000000007 );
+ TEST_RR_OP( 5, slt, 0, 0x0000000000000007, 0x0000000000000003 );
+
+ TEST_RR_OP( 6, slt, 0, 0x0000000000000000, 0xffffffffffff8000 );
+ TEST_RR_OP( 7, slt, 1, 0xffffffff80000000, 0x0000000000000000 );
+ TEST_RR_OP( 8, slt, 1, 0xffffffff80000000, 0xffffffffffff8000 );
+
+ TEST_RR_OP( 9, slt, 1, 0x0000000000000000, 0x0000000000007fff );
+ TEST_RR_OP( 10, slt, 0, 0x000000007fffffff, 0x0000000000000000 );
+ TEST_RR_OP( 11, slt, 0, 0x000000007fffffff, 0x0000000000007fff );
+
+ TEST_RR_OP( 12, slt, 1, 0xffffffff80000000, 0x0000000000007fff );
+ TEST_RR_OP( 13, slt, 0, 0x000000007fffffff, 0xffffffffffff8000 );
+
+ TEST_RR_OP( 14, slt, 0, 0x0000000000000000, 0xffffffffffffffff );
+ TEST_RR_OP( 15, slt, 1, 0xffffffffffffffff, 0x0000000000000001 );
+ TEST_RR_OP( 16, slt, 0, 0xffffffffffffffff, 0xffffffffffffffff );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 17, slt, 0, 14, 13 );
+ TEST_RR_SRC2_EQ_DEST( 18, slt, 1, 11, 13 );
+ TEST_RR_SRC12_EQ_DEST( 19, slt, 0, 13 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 20, 0, slt, 1, 11, 13 );
+ TEST_RR_DEST_BYPASS( 21, 1, slt, 0, 14, 13 );
+ TEST_RR_DEST_BYPASS( 22, 2, slt, 1, 12, 13 );
+
+ TEST_RR_SRC12_BYPASS( 23, 0, 0, slt, 0, 14, 13 );
+ TEST_RR_SRC12_BYPASS( 24, 0, 1, slt, 1, 11, 13 );
+ TEST_RR_SRC12_BYPASS( 25, 0, 2, slt, 0, 15, 13 );
+ TEST_RR_SRC12_BYPASS( 26, 1, 0, slt, 1, 10, 13 );
+ TEST_RR_SRC12_BYPASS( 27, 1, 1, slt, 0, 16, 13 );
+ TEST_RR_SRC12_BYPASS( 28, 2, 0, slt, 1, 9, 13 );
+
+ TEST_RR_SRC21_BYPASS( 29, 0, 0, slt, 0, 17, 13 );
+ TEST_RR_SRC21_BYPASS( 30, 0, 1, slt, 1, 8, 13 );
+ TEST_RR_SRC21_BYPASS( 31, 0, 2, slt, 0, 18, 13 );
+ TEST_RR_SRC21_BYPASS( 32, 1, 0, slt, 1, 7, 13 );
+ TEST_RR_SRC21_BYPASS( 33, 1, 1, slt, 0, 19, 13 );
+ TEST_RR_SRC21_BYPASS( 34, 2, 0, slt, 1, 6, 13 );
+
+ TEST_RR_ZEROSRC1( 35, slt, 0, -1 );
+ TEST_RR_ZEROSRC2( 36, slt, 1, -1 );
+ TEST_RR_ZEROSRC12( 37, slt, 0 );
+ TEST_RR_ZERODEST( 38, slt, 16, 30 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/slti.S b/tests/riscv-tests/rv32ui/slti.S
@@ -0,0 +1,70 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# slti.S
+#-----------------------------------------------------------------------------
+#
+# Test slti instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_OP( 2, slti, 0, 0x0000000000000000, 0x000 );
+ TEST_IMM_OP( 3, slti, 0, 0x0000000000000001, 0x001 );
+ TEST_IMM_OP( 4, slti, 1, 0x0000000000000003, 0x007 );
+ TEST_IMM_OP( 5, slti, 0, 0x0000000000000007, 0x003 );
+
+ TEST_IMM_OP( 6, slti, 0, 0x0000000000000000, 0x800 );
+ TEST_IMM_OP( 7, slti, 1, 0xffffffff80000000, 0x000 );
+ TEST_IMM_OP( 8, slti, 1, 0xffffffff80000000, 0x800 );
+
+ TEST_IMM_OP( 9, slti, 1, 0x0000000000000000, 0x7ff );
+ TEST_IMM_OP( 10, slti, 0, 0x000000007fffffff, 0x000 );
+ TEST_IMM_OP( 11, slti, 0, 0x000000007fffffff, 0x7ff );
+
+ TEST_IMM_OP( 12, slti, 1, 0xffffffff80000000, 0x7ff );
+ TEST_IMM_OP( 13, slti, 0, 0x000000007fffffff, 0x800 );
+
+ TEST_IMM_OP( 14, slti, 0, 0x0000000000000000, 0xfff );
+ TEST_IMM_OP( 15, slti, 1, 0xffffffffffffffff, 0x001 );
+ TEST_IMM_OP( 16, slti, 0, 0xffffffffffffffff, 0xfff );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_SRC1_EQ_DEST( 17, slti, 1, 11, 13 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_DEST_BYPASS( 18, 0, slti, 0, 15, 10 );
+ TEST_IMM_DEST_BYPASS( 19, 1, slti, 1, 10, 16 );
+ TEST_IMM_DEST_BYPASS( 20, 2, slti, 0, 16, 9 );
+
+ TEST_IMM_SRC1_BYPASS( 21, 0, slti, 1, 11, 15 );
+ TEST_IMM_SRC1_BYPASS( 22, 1, slti, 0, 17, 8 );
+ TEST_IMM_SRC1_BYPASS( 23, 2, slti, 1, 12, 14 );
+
+ TEST_IMM_ZEROSRC1( 24, slti, 0, 0xfff );
+ TEST_IMM_ZERODEST( 25, slti, 0x00ff00ff, 0xfff );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/sltiu.S b/tests/riscv-tests/rv32ui/sltiu.S
@@ -0,0 +1,70 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sltiu.S
+#-----------------------------------------------------------------------------
+#
+# Test sltiu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_OP( 2, sltiu, 0, 0x0000000000000000, 0x000 );
+ TEST_IMM_OP( 3, sltiu, 0, 0x0000000000000001, 0x001 );
+ TEST_IMM_OP( 4, sltiu, 1, 0x0000000000000003, 0x007 );
+ TEST_IMM_OP( 5, sltiu, 0, 0x0000000000000007, 0x003 );
+
+ TEST_IMM_OP( 6, sltiu, 1, 0x0000000000000000, 0x800 );
+ TEST_IMM_OP( 7, sltiu, 0, 0xffffffff80000000, 0x000 );
+ TEST_IMM_OP( 8, sltiu, 1, 0xffffffff80000000, 0x800 );
+
+ TEST_IMM_OP( 9, sltiu, 1, 0x0000000000000000, 0x7ff );
+ TEST_IMM_OP( 10, sltiu, 0, 0x000000007fffffff, 0x000 );
+ TEST_IMM_OP( 11, sltiu, 0, 0x000000007fffffff, 0x7ff );
+
+ TEST_IMM_OP( 12, sltiu, 0, 0xffffffff80000000, 0x7ff );
+ TEST_IMM_OP( 13, sltiu, 1, 0x000000007fffffff, 0x800 );
+
+ TEST_IMM_OP( 14, sltiu, 1, 0x0000000000000000, 0xfff );
+ TEST_IMM_OP( 15, sltiu, 0, 0xffffffffffffffff, 0x001 );
+ TEST_IMM_OP( 16, sltiu, 0, 0xffffffffffffffff, 0xfff );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_SRC1_EQ_DEST( 17, sltiu, 1, 11, 13 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_DEST_BYPASS( 18, 0, sltiu, 0, 15, 10 );
+ TEST_IMM_DEST_BYPASS( 19, 1, sltiu, 1, 10, 16 );
+ TEST_IMM_DEST_BYPASS( 20, 2, sltiu, 0, 16, 9 );
+
+ TEST_IMM_SRC1_BYPASS( 21, 0, sltiu, 1, 11, 15 );
+ TEST_IMM_SRC1_BYPASS( 22, 1, sltiu, 0, 17, 8 );
+ TEST_IMM_SRC1_BYPASS( 23, 2, sltiu, 1, 12, 14 );
+
+ TEST_IMM_ZEROSRC1( 24, sltiu, 1, 0xfff );
+ TEST_IMM_ZERODEST( 25, sltiu, 0x00ff00ff, 0xfff );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/sltu.S b/tests/riscv-tests/rv32ui/sltu.S
@@ -0,0 +1,84 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sltu.S
+#-----------------------------------------------------------------------------
+#
+# Test sltu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, sltu, 0, 0x00000000, 0x00000000 );
+ TEST_RR_OP( 3, sltu, 0, 0x00000001, 0x00000001 );
+ TEST_RR_OP( 4, sltu, 1, 0x00000003, 0x00000007 );
+ TEST_RR_OP( 5, sltu, 0, 0x00000007, 0x00000003 );
+
+ TEST_RR_OP( 6, sltu, 1, 0x00000000, 0xffff8000 );
+ TEST_RR_OP( 7, sltu, 0, 0x80000000, 0x00000000 );
+ TEST_RR_OP( 8, sltu, 1, 0x80000000, 0xffff8000 );
+
+ TEST_RR_OP( 9, sltu, 1, 0x00000000, 0x00007fff );
+ TEST_RR_OP( 10, sltu, 0, 0x7fffffff, 0x00000000 );
+ TEST_RR_OP( 11, sltu, 0, 0x7fffffff, 0x00007fff );
+
+ TEST_RR_OP( 12, sltu, 0, 0x80000000, 0x00007fff );
+ TEST_RR_OP( 13, sltu, 1, 0x7fffffff, 0xffff8000 );
+
+ TEST_RR_OP( 14, sltu, 1, 0x00000000, 0xffffffff );
+ TEST_RR_OP( 15, sltu, 0, 0xffffffff, 0x00000001 );
+ TEST_RR_OP( 16, sltu, 0, 0xffffffff, 0xffffffff );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 17, sltu, 0, 14, 13 );
+ TEST_RR_SRC2_EQ_DEST( 18, sltu, 1, 11, 13 );
+ TEST_RR_SRC12_EQ_DEST( 19, sltu, 0, 13 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 20, 0, sltu, 1, 11, 13 );
+ TEST_RR_DEST_BYPASS( 21, 1, sltu, 0, 14, 13 );
+ TEST_RR_DEST_BYPASS( 22, 2, sltu, 1, 12, 13 );
+
+ TEST_RR_SRC12_BYPASS( 23, 0, 0, sltu, 0, 14, 13 );
+ TEST_RR_SRC12_BYPASS( 24, 0, 1, sltu, 1, 11, 13 );
+ TEST_RR_SRC12_BYPASS( 25, 0, 2, sltu, 0, 15, 13 );
+ TEST_RR_SRC12_BYPASS( 26, 1, 0, sltu, 1, 10, 13 );
+ TEST_RR_SRC12_BYPASS( 27, 1, 1, sltu, 0, 16, 13 );
+ TEST_RR_SRC12_BYPASS( 28, 2, 0, sltu, 1, 9, 13 );
+
+ TEST_RR_SRC21_BYPASS( 29, 0, 0, sltu, 0, 17, 13 );
+ TEST_RR_SRC21_BYPASS( 30, 0, 1, sltu, 1, 8, 13 );
+ TEST_RR_SRC21_BYPASS( 31, 0, 2, sltu, 0, 18, 13 );
+ TEST_RR_SRC21_BYPASS( 32, 1, 0, sltu, 1, 7, 13 );
+ TEST_RR_SRC21_BYPASS( 33, 1, 1, sltu, 0, 19, 13 );
+ TEST_RR_SRC21_BYPASS( 34, 2, 0, sltu, 1, 6, 13 );
+
+ TEST_RR_ZEROSRC1( 35, sltu, 1, -1 );
+ TEST_RR_ZEROSRC2( 36, sltu, 0, -1 );
+ TEST_RR_ZEROSRC12( 37, sltu, 0 );
+ TEST_RR_ZERODEST( 38, sltu, 16, 30 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/sra.S b/tests/riscv-tests/rv32ui/sra.S
@@ -0,0 +1,90 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sra.S
+#-----------------------------------------------------------------------------
+#
+# Test sra instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, sra, 0xffffffff80000000, 0xffffffff80000000, 0 );
+ TEST_RR_OP( 3, sra, 0xffffffffc0000000, 0xffffffff80000000, 1 );
+ TEST_RR_OP( 4, sra, 0xffffffffff000000, 0xffffffff80000000, 7 );
+ TEST_RR_OP( 5, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+ TEST_RR_OP( 6, sra, 0xffffffffffffffff, 0xffffffff80000001, 31 );
+
+ TEST_RR_OP( 7, sra, 0x000000007fffffff, 0x000000007fffffff, 0 );
+ TEST_RR_OP( 8, sra, 0x000000003fffffff, 0x000000007fffffff, 1 );
+ TEST_RR_OP( 9, sra, 0x0000000000ffffff, 0x000000007fffffff, 7 );
+ TEST_RR_OP( 10, sra, 0x000000000001ffff, 0x000000007fffffff, 14 );
+ TEST_RR_OP( 11, sra, 0x0000000000000000, 0x000000007fffffff, 31 );
+
+ TEST_RR_OP( 12, sra, 0xffffffff81818181, 0xffffffff81818181, 0 );
+ TEST_RR_OP( 13, sra, 0xffffffffc0c0c0c0, 0xffffffff81818181, 1 );
+ TEST_RR_OP( 14, sra, 0xffffffffff030303, 0xffffffff81818181, 7 );
+ TEST_RR_OP( 15, sra, 0xfffffffffffe0606, 0xffffffff81818181, 14 );
+ TEST_RR_OP( 16, sra, 0xffffffffffffffff, 0xffffffff81818181, 31 );
+
+ # Verify that shifts only use bottom six(rv64) or five(rv32) bits
+
+ TEST_RR_OP( 17, sra, 0xffffffff81818181, 0xffffffff81818181, 0xffffffffffffffc0 );
+ TEST_RR_OP( 18, sra, 0xffffffffc0c0c0c0, 0xffffffff81818181, 0xffffffffffffffc1 );
+ TEST_RR_OP( 19, sra, 0xffffffffff030303, 0xffffffff81818181, 0xffffffffffffffc7 );
+ TEST_RR_OP( 20, sra, 0xfffffffffffe0606, 0xffffffff81818181, 0xffffffffffffffce );
+ TEST_RR_OP( 21, sra, 0xffffffffffffffff, 0xffffffff81818181, 0xffffffffffffffff );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 22, sra, 0xffffffffff000000, 0xffffffff80000000, 7 );
+ TEST_RR_SRC2_EQ_DEST( 23, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+ TEST_RR_SRC12_EQ_DEST( 24, sra, 0, 7 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 25, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 );
+ TEST_RR_DEST_BYPASS( 26, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+ TEST_RR_DEST_BYPASS( 27, 2, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 );
+
+ TEST_RR_SRC12_BYPASS( 28, 0, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 );
+ TEST_RR_SRC12_BYPASS( 29, 0, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+ TEST_RR_SRC12_BYPASS( 30, 0, 2, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 );
+ TEST_RR_SRC12_BYPASS( 31, 1, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 );
+ TEST_RR_SRC12_BYPASS( 32, 1, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+ TEST_RR_SRC12_BYPASS( 33, 2, 0, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 );
+
+ TEST_RR_SRC21_BYPASS( 34, 0, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 );
+ TEST_RR_SRC21_BYPASS( 35, 0, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+ TEST_RR_SRC21_BYPASS( 36, 0, 2, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 );
+ TEST_RR_SRC21_BYPASS( 37, 1, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 );
+ TEST_RR_SRC21_BYPASS( 38, 1, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+ TEST_RR_SRC21_BYPASS( 39, 2, 0, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 );
+
+ TEST_RR_ZEROSRC1( 40, sra, 0, 15 );
+ TEST_RR_ZEROSRC2( 41, sra, 32, 32 );
+ TEST_RR_ZEROSRC12( 42, sra, 0 );
+ TEST_RR_ZERODEST( 43, sra, 1024, 2048 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/srai.S b/tests/riscv-tests/rv32ui/srai.S
@@ -0,0 +1,68 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# srai.S
+#-----------------------------------------------------------------------------
+#
+# Test srai instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_OP( 2, srai, 0xffffff8000000000, 0xffffff8000000000, 0 );
+ TEST_IMM_OP( 3, srai, 0xffffffffc0000000, 0xffffffff80000000, 1 );
+ TEST_IMM_OP( 4, srai, 0xffffffffff000000, 0xffffffff80000000, 7 );
+ TEST_IMM_OP( 5, srai, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+ TEST_IMM_OP( 6, srai, 0xffffffffffffffff, 0xffffffff80000001, 31 );
+
+ TEST_IMM_OP( 7, srai, 0x000000007fffffff, 0x000000007fffffff, 0 );
+ TEST_IMM_OP( 8, srai, 0x000000003fffffff, 0x000000007fffffff, 1 );
+ TEST_IMM_OP( 9, srai, 0x0000000000ffffff, 0x000000007fffffff, 7 );
+ TEST_IMM_OP( 10, srai, 0x000000000001ffff, 0x000000007fffffff, 14 );
+ TEST_IMM_OP( 11, srai, 0x0000000000000000, 0x000000007fffffff, 31 );
+
+ TEST_IMM_OP( 12, srai, 0xffffffff81818181, 0xffffffff81818181, 0 );
+ TEST_IMM_OP( 13, srai, 0xffffffffc0c0c0c0, 0xffffffff81818181, 1 );
+ TEST_IMM_OP( 14, srai, 0xffffffffff030303, 0xffffffff81818181, 7 );
+ TEST_IMM_OP( 15, srai, 0xfffffffffffe0606, 0xffffffff81818181, 14 );
+ TEST_IMM_OP( 16, srai, 0xffffffffffffffff, 0xffffffff81818181, 31 );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_SRC1_EQ_DEST( 17, srai, 0xffffffffff000000, 0xffffffff80000000, 7 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_DEST_BYPASS( 18, 0, srai, 0xffffffffff000000, 0xffffffff80000000, 7 );
+ TEST_IMM_DEST_BYPASS( 19, 1, srai, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+ TEST_IMM_DEST_BYPASS( 20, 2, srai, 0xffffffffffffffff, 0xffffffff80000001, 31 );
+
+ TEST_IMM_SRC1_BYPASS( 21, 0, srai, 0xffffffffff000000, 0xffffffff80000000, 7 );
+ TEST_IMM_SRC1_BYPASS( 22, 1, srai, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+ TEST_IMM_SRC1_BYPASS( 23, 2, srai, 0xffffffffffffffff, 0xffffffff80000001, 31 );
+
+ TEST_IMM_ZEROSRC1( 24, srai, 0, 4 );
+ TEST_IMM_ZERODEST( 25, srai, 33, 10 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/sraiw.S b/tests/riscv-tests/rv32ui/sraiw.S
@@ -0,0 +1,78 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sraiw.S
+#-----------------------------------------------------------------------------
+#
+# Test sraiw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_OP( 2, sraiw, 0xffffffff80000000, 0xffffffff80000000, 0 );
+ TEST_IMM_OP( 3, sraiw, 0xffffffffc0000000, 0xffffffff80000000, 1 );
+ TEST_IMM_OP( 4, sraiw, 0xffffffffff000000, 0xffffffff80000000, 7 );
+ TEST_IMM_OP( 5, sraiw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+ TEST_IMM_OP( 6, sraiw, 0xffffffffffffffff, 0xffffffff80000001, 31 );
+
+ TEST_IMM_OP( 7, sraiw, 0x000000007fffffff, 0x000000007fffffff, 0 );
+ TEST_IMM_OP( 8, sraiw, 0x000000003fffffff, 0x000000007fffffff, 1 );
+ TEST_IMM_OP( 9, sraiw, 0x0000000000ffffff, 0x000000007fffffff, 7 );
+ TEST_IMM_OP( 10, sraiw, 0x000000000001ffff, 0x000000007fffffff, 14 );
+ TEST_IMM_OP( 11, sraiw, 0x0000000000000000, 0x000000007fffffff, 31 );
+
+ TEST_IMM_OP( 12, sraiw, 0xffffffff81818181, 0xffffffff81818181, 0 );
+ TEST_IMM_OP( 13, sraiw, 0xffffffffc0c0c0c0, 0xffffffff81818181, 1 );
+ TEST_IMM_OP( 14, sraiw, 0xffffffffff030303, 0xffffffff81818181, 7 );
+ TEST_IMM_OP( 15, sraiw, 0xfffffffffffe0606, 0xffffffff81818181, 14 );
+ TEST_IMM_OP( 16, sraiw, 0xffffffffffffffff, 0xffffffff81818181, 31 );
+
+ # Verify that shifts ignore top 32 (using true 64-bit values)
+
+ TEST_IMM_OP( 44, sraiw, 0x0000000012345678, 0xffffffff12345678, 0 );
+ TEST_IMM_OP( 45, sraiw, 0x0000000001234567, 0xffffffff12345678, 4 );
+ TEST_IMM_OP( 46, sraiw, 0xffffffff92345678, 0x0000000092345678, 0 );
+ TEST_IMM_OP( 47, sraiw, 0xfffffffff9234567, 0x0000000092345678, 4 );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_SRC1_EQ_DEST( 17, sraiw, 0xffffffffff000000, 0xffffffff80000000, 7 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_DEST_BYPASS( 18, 0, sraiw, 0xffffffffff000000, 0xffffffff80000000, 7 );
+ TEST_IMM_DEST_BYPASS( 19, 1, sraiw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+ TEST_IMM_DEST_BYPASS( 20, 2, sraiw, 0xffffffffffffffff, 0xffffffff80000001, 31 );
+
+ TEST_IMM_SRC1_BYPASS( 21, 0, sraiw, 0xffffffffff000000, 0xffffffff80000000, 7 );
+ TEST_IMM_SRC1_BYPASS( 22, 1, sraiw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+ TEST_IMM_SRC1_BYPASS( 23, 2, sraiw, 0xffffffffffffffff, 0xffffffff80000001, 31 );
+
+ TEST_IMM_ZEROSRC1( 24, sraiw, 0, 31 );
+ TEST_IMM_ZERODEST( 25, sraiw, 31, 28 );
+
+ TEST_IMM_OP( 26, sraiw, 0x0000000000000000, 0x00e0000000000000, 28)
+ TEST_IMM_OP( 27, sraiw, 0xffffffffff000000, 0x00000000f0000000, 4)
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/sraw.S b/tests/riscv-tests/rv32ui/sraw.S
@@ -0,0 +1,97 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sraw.S
+#-----------------------------------------------------------------------------
+#
+# Test sraw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, sraw, 0xffffffff80000000, 0xffffffff80000000, 0 );
+ TEST_RR_OP( 3, sraw, 0xffffffffc0000000, 0xffffffff80000000, 1 );
+ TEST_RR_OP( 4, sraw, 0xffffffffff000000, 0xffffffff80000000, 7 );
+ TEST_RR_OP( 5, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+ TEST_RR_OP( 6, sraw, 0xffffffffffffffff, 0xffffffff80000001, 31 );
+
+ TEST_RR_OP( 7, sraw, 0x000000007fffffff, 0x000000007fffffff, 0 );
+ TEST_RR_OP( 8, sraw, 0x000000003fffffff, 0x000000007fffffff, 1 );
+ TEST_RR_OP( 9, sraw, 0x0000000000ffffff, 0x000000007fffffff, 7 );
+ TEST_RR_OP( 10, sraw, 0x000000000001ffff, 0x000000007fffffff, 14 );
+ TEST_RR_OP( 11, sraw, 0x0000000000000000, 0x000000007fffffff, 31 );
+
+ TEST_RR_OP( 12, sraw, 0xffffffff81818181, 0xffffffff81818181, 0 );
+ TEST_RR_OP( 13, sraw, 0xffffffffc0c0c0c0, 0xffffffff81818181, 1 );
+ TEST_RR_OP( 14, sraw, 0xffffffffff030303, 0xffffffff81818181, 7 );
+ TEST_RR_OP( 15, sraw, 0xfffffffffffe0606, 0xffffffff81818181, 14 );
+ TEST_RR_OP( 16, sraw, 0xffffffffffffffff, 0xffffffff81818181, 31 );
+
+ # Verify that shifts only use bottom five bits
+
+ TEST_RR_OP( 17, sraw, 0xffffffff81818181, 0xffffffff81818181, 0xffffffffffffffe0 );
+ TEST_RR_OP( 18, sraw, 0xffffffffc0c0c0c0, 0xffffffff81818181, 0xffffffffffffffe1 );
+ TEST_RR_OP( 19, sraw, 0xffffffffff030303, 0xffffffff81818181, 0xffffffffffffffe7 );
+ TEST_RR_OP( 20, sraw, 0xfffffffffffe0606, 0xffffffff81818181, 0xffffffffffffffee );
+ TEST_RR_OP( 21, sraw, 0xffffffffffffffff, 0xffffffff81818181, 0xffffffffffffffff );
+
+ # Verify that shifts ignore top 32 (using true 64-bit values)
+
+ TEST_RR_OP( 44, sraw, 0x0000000012345678, 0xffffffff12345678, 0 );
+ TEST_RR_OP( 45, sraw, 0x0000000001234567, 0xffffffff12345678, 4 );
+ TEST_RR_OP( 46, sraw, 0xffffffff92345678, 0x0000000092345678, 0 );
+ TEST_RR_OP( 47, sraw, 0xfffffffff9234567, 0x0000000092345678, 4 );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 22, sraw, 0xffffffffff000000, 0xffffffff80000000, 7 );
+ TEST_RR_SRC2_EQ_DEST( 23, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+ TEST_RR_SRC12_EQ_DEST( 24, sraw, 0, 7 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 25, 0, sraw, 0xffffffffff000000, 0xffffffff80000000, 7 );
+ TEST_RR_DEST_BYPASS( 26, 1, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+ TEST_RR_DEST_BYPASS( 27, 2, sraw, 0xffffffffffffffff, 0xffffffff80000000, 31 );
+
+ TEST_RR_SRC12_BYPASS( 28, 0, 0, sraw, 0xffffffffff000000, 0xffffffff80000000, 7 );
+ TEST_RR_SRC12_BYPASS( 29, 0, 1, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+ TEST_RR_SRC12_BYPASS( 30, 0, 2, sraw, 0xffffffffffffffff, 0xffffffff80000000, 31 );
+ TEST_RR_SRC12_BYPASS( 31, 1, 0, sraw, 0xffffffffff000000, 0xffffffff80000000, 7 );
+ TEST_RR_SRC12_BYPASS( 32, 1, 1, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+ TEST_RR_SRC12_BYPASS( 33, 2, 0, sraw, 0xffffffffffffffff, 0xffffffff80000000, 31 );
+
+ TEST_RR_SRC21_BYPASS( 34, 0, 0, sraw, 0xffffffffff000000, 0xffffffff80000000, 7 );
+ TEST_RR_SRC21_BYPASS( 35, 0, 1, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+ TEST_RR_SRC21_BYPASS( 36, 0, 2, sraw, 0xffffffffffffffff, 0xffffffff80000000, 31 );
+ TEST_RR_SRC21_BYPASS( 37, 1, 0, sraw, 0xffffffffff000000, 0xffffffff80000000, 7 );
+ TEST_RR_SRC21_BYPASS( 38, 1, 1, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+ TEST_RR_SRC21_BYPASS( 39, 2, 0, sraw, 0xffffffffffffffff, 0xffffffff80000000, 31 );
+
+ TEST_RR_ZEROSRC1( 40, sraw, 0, 15 );
+ TEST_RR_ZEROSRC2( 41, sraw, 32, 32 );
+ TEST_RR_ZEROSRC12( 42, sraw, 0 );
+ TEST_RR_ZERODEST( 43, sraw, 1024, 2048 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/srl.S b/tests/riscv-tests/rv32ui/srl.S
@@ -0,0 +1,93 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# srl.S
+#-----------------------------------------------------------------------------
+#
+# Test srl instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+#define TEST_SRL(n, v, a) \
+ TEST_RR_OP(n, srl, ((v) & ((1 << (__riscv_xlen-1) << 1) - 1)) >> (a), v, a)
+
+ TEST_SRL( 2, 0xffffffff80000000, 0 );
+ TEST_SRL( 3, 0xffffffff80000000, 1 );
+ TEST_SRL( 4, 0xffffffff80000000, 7 );
+ TEST_SRL( 5, 0xffffffff80000000, 14 );
+ TEST_SRL( 6, 0xffffffff80000001, 31 );
+
+ TEST_SRL( 7, 0xffffffffffffffff, 0 );
+ TEST_SRL( 8, 0xffffffffffffffff, 1 );
+ TEST_SRL( 9, 0xffffffffffffffff, 7 );
+ TEST_SRL( 10, 0xffffffffffffffff, 14 );
+ TEST_SRL( 11, 0xffffffffffffffff, 31 );
+
+ TEST_SRL( 12, 0x0000000021212121, 0 );
+ TEST_SRL( 13, 0x0000000021212121, 1 );
+ TEST_SRL( 14, 0x0000000021212121, 7 );
+ TEST_SRL( 15, 0x0000000021212121, 14 );
+ TEST_SRL( 16, 0x0000000021212121, 31 );
+
+ # Verify that shifts only use bottom six(rv64) or five(rv32) bits
+
+ TEST_RR_OP( 17, srl, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 );
+ TEST_RR_OP( 18, srl, 0x0000000010909090, 0x0000000021212121, 0xffffffffffffffc1 );
+ TEST_RR_OP( 19, srl, 0x0000000000424242, 0x0000000021212121, 0xffffffffffffffc7 );
+ TEST_RR_OP( 20, srl, 0x0000000000008484, 0x0000000021212121, 0xffffffffffffffce );
+ TEST_RR_OP( 21, srl, 0x0000000000000000, 0x0000000021212121, 0xffffffffffffffff );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 22, srl, 0x01000000, 0x80000000, 7 );
+ TEST_RR_SRC2_EQ_DEST( 23, srl, 0x00020000, 0x80000000, 14 );
+ TEST_RR_SRC12_EQ_DEST( 24, srl, 0, 7 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 25, 0, srl, 0x01000000, 0x80000000, 7 );
+ TEST_RR_DEST_BYPASS( 26, 1, srl, 0x00020000, 0x80000000, 14 );
+ TEST_RR_DEST_BYPASS( 27, 2, srl, 0x00000001, 0x80000000, 31 );
+
+ TEST_RR_SRC12_BYPASS( 28, 0, 0, srl, 0x01000000, 0x80000000, 7 );
+ TEST_RR_SRC12_BYPASS( 29, 0, 1, srl, 0x00020000, 0x80000000, 14 );
+ TEST_RR_SRC12_BYPASS( 30, 0, 2, srl, 0x00000001, 0x80000000, 31 );
+ TEST_RR_SRC12_BYPASS( 31, 1, 0, srl, 0x01000000, 0x80000000, 7 );
+ TEST_RR_SRC12_BYPASS( 32, 1, 1, srl, 0x00020000, 0x80000000, 14 );
+ TEST_RR_SRC12_BYPASS( 33, 2, 0, srl, 0x00000001, 0x80000000, 31 );
+
+ TEST_RR_SRC21_BYPASS( 34, 0, 0, srl, 0x01000000, 0x80000000, 7 );
+ TEST_RR_SRC21_BYPASS( 35, 0, 1, srl, 0x00020000, 0x80000000, 14 );
+ TEST_RR_SRC21_BYPASS( 36, 0, 2, srl, 0x00000001, 0x80000000, 31 );
+ TEST_RR_SRC21_BYPASS( 37, 1, 0, srl, 0x01000000, 0x80000000, 7 );
+ TEST_RR_SRC21_BYPASS( 38, 1, 1, srl, 0x00020000, 0x80000000, 14 );
+ TEST_RR_SRC21_BYPASS( 39, 2, 0, srl, 0x00000001, 0x80000000, 31 );
+
+ TEST_RR_ZEROSRC1( 40, srl, 0, 15 );
+ TEST_RR_ZEROSRC2( 41, srl, 32, 32 );
+ TEST_RR_ZEROSRC12( 42, srl, 0 );
+ TEST_RR_ZERODEST( 43, srl, 1024, 2048 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/srli.S b/tests/riscv-tests/rv32ui/srli.S
@@ -0,0 +1,71 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# srli.S
+#-----------------------------------------------------------------------------
+#
+# Test srli instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+#define TEST_SRLI(n, v, a) \
+ TEST_IMM_OP(n, srli, ((v) & ((1 << (__riscv_xlen-1) << 1) - 1)) >> (a), v, a)
+
+ TEST_SRLI( 2, 0xffffffff80000000, 0 );
+ TEST_SRLI( 3, 0xffffffff80000000, 1 );
+ TEST_SRLI( 4, 0xffffffff80000000, 7 );
+ TEST_SRLI( 5, 0xffffffff80000000, 14 );
+ TEST_SRLI( 6, 0xffffffff80000001, 31 );
+
+ TEST_SRLI( 7, 0xffffffffffffffff, 0 );
+ TEST_SRLI( 8, 0xffffffffffffffff, 1 );
+ TEST_SRLI( 9, 0xffffffffffffffff, 7 );
+ TEST_SRLI( 10, 0xffffffffffffffff, 14 );
+ TEST_SRLI( 11, 0xffffffffffffffff, 31 );
+
+ TEST_SRLI( 12, 0x0000000021212121, 0 );
+ TEST_SRLI( 13, 0x0000000021212121, 1 );
+ TEST_SRLI( 14, 0x0000000021212121, 7 );
+ TEST_SRLI( 15, 0x0000000021212121, 14 );
+ TEST_SRLI( 16, 0x0000000021212121, 31 );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_SRC1_EQ_DEST( 17, srli, 0x01000000, 0x80000000, 7 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_DEST_BYPASS( 18, 0, srli, 0x01000000, 0x80000000, 7 );
+ TEST_IMM_DEST_BYPASS( 19, 1, srli, 0x00020000, 0x80000000, 14 );
+ TEST_IMM_DEST_BYPASS( 20, 2, srli, 0x00000001, 0x80000001, 31 );
+
+ TEST_IMM_SRC1_BYPASS( 21, 0, srli, 0x01000000, 0x80000000, 7 );
+ TEST_IMM_SRC1_BYPASS( 22, 1, srli, 0x00020000, 0x80000000, 14 );
+ TEST_IMM_SRC1_BYPASS( 23, 2, srli, 0x00000001, 0x80000001, 31 );
+
+ TEST_IMM_ZEROSRC1( 24, srli, 0, 4 );
+ TEST_IMM_ZERODEST( 25, srli, 33, 10 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/srliw.S b/tests/riscv-tests/rv32ui/srliw.S
@@ -0,0 +1,75 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# srliw.S
+#-----------------------------------------------------------------------------
+#
+# Test srliw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_OP( 2, srliw, 0xffffffff80000000, 0xffffffff80000000, 0 );
+ TEST_IMM_OP( 3, srliw, 0x0000000040000000, 0xffffffff80000000, 1 );
+ TEST_IMM_OP( 4, srliw, 0x0000000001000000, 0xffffffff80000000, 7 );
+ TEST_IMM_OP( 5, srliw, 0x0000000000020000, 0xffffffff80000000, 14 );
+ TEST_IMM_OP( 6, srliw, 0x0000000000000001, 0xffffffff80000001, 31 );
+
+ TEST_IMM_OP( 7, srliw, 0xffffffffffffffff, 0xffffffffffffffff, 0 );
+ TEST_IMM_OP( 8, srliw, 0x000000007fffffff, 0xffffffffffffffff, 1 );
+ TEST_IMM_OP( 9, srliw, 0x0000000001ffffff, 0xffffffffffffffff, 7 );
+ TEST_IMM_OP( 10, srliw, 0x000000000003ffff, 0xffffffffffffffff, 14 );
+ TEST_IMM_OP( 11, srliw, 0x0000000000000001, 0xffffffffffffffff, 31 );
+
+ TEST_IMM_OP( 12, srliw, 0x0000000021212121, 0x0000000021212121, 0 );
+ TEST_IMM_OP( 13, srliw, 0x0000000010909090, 0x0000000021212121, 1 );
+ TEST_IMM_OP( 14, srliw, 0x0000000000424242, 0x0000000021212121, 7 );
+ TEST_IMM_OP( 15, srliw, 0x0000000000008484, 0x0000000021212121, 14 );
+ TEST_IMM_OP( 16, srliw, 0x0000000000000000, 0x0000000021212121, 31 );
+
+ # Verify that shifts ignore top 32 (using true 64-bit values)
+
+ TEST_IMM_OP( 44, srliw, 0x0000000012345678, 0xffffffff12345678, 0 );
+ TEST_IMM_OP( 45, srliw, 0x0000000001234567, 0xffffffff12345678, 4 );
+ TEST_IMM_OP( 46, srliw, 0xffffffff92345678, 0x0000000092345678, 0 );
+ TEST_IMM_OP( 47, srliw, 0x0000000009234567, 0x0000000092345678, 4 );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_SRC1_EQ_DEST( 17, srliw, 0x0000000001000000, 0xffffffff80000000, 7 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_DEST_BYPASS( 18, 0, srliw, 0x0000000001000000, 0xffffffff80000000, 7 );
+ TEST_IMM_DEST_BYPASS( 19, 1, srliw, 0x0000000000020000, 0xffffffff80000000, 14 );
+ TEST_IMM_DEST_BYPASS( 20, 2, srliw, 0x0000000000000001, 0xffffffff80000001, 31 );
+
+ TEST_IMM_SRC1_BYPASS( 21, 0, srliw, 0x0000000001000000, 0xffffffff80000000, 7 );
+ TEST_IMM_SRC1_BYPASS( 22, 1, srliw, 0x0000000000020000, 0xffffffff80000000, 14 );
+ TEST_IMM_SRC1_BYPASS( 23, 2, srliw, 0x0000000000000001, 0xffffffff80000001, 31 );
+
+ TEST_IMM_ZEROSRC1( 24, srliw, 0, 31 );
+ TEST_IMM_ZERODEST( 25, srliw, 31, 28 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/srlw.S b/tests/riscv-tests/rv32ui/srlw.S
@@ -0,0 +1,97 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# srlw.S
+#-----------------------------------------------------------------------------
+#
+# Test srlw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, srlw, 0xffffffff80000000, 0xffffffff80000000, 0 );
+ TEST_RR_OP( 3, srlw, 0x0000000040000000, 0xffffffff80000000, 1 );
+ TEST_RR_OP( 4, srlw, 0x0000000001000000, 0xffffffff80000000, 7 );
+ TEST_RR_OP( 5, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
+ TEST_RR_OP( 6, srlw, 0x0000000000000001, 0xffffffff80000001, 31 );
+
+ TEST_RR_OP( 7, srlw, 0xffffffffffffffff, 0xffffffffffffffff, 0 );
+ TEST_RR_OP( 8, srlw, 0x000000007fffffff, 0xffffffffffffffff, 1 );
+ TEST_RR_OP( 9, srlw, 0x0000000001ffffff, 0xffffffffffffffff, 7 );
+ TEST_RR_OP( 10, srlw, 0x000000000003ffff, 0xffffffffffffffff, 14 );
+ TEST_RR_OP( 11, srlw, 0x0000000000000001, 0xffffffffffffffff, 31 );
+
+ TEST_RR_OP( 12, srlw, 0x0000000021212121, 0x0000000021212121, 0 );
+ TEST_RR_OP( 13, srlw, 0x0000000010909090, 0x0000000021212121, 1 );
+ TEST_RR_OP( 14, srlw, 0x0000000000424242, 0x0000000021212121, 7 );
+ TEST_RR_OP( 15, srlw, 0x0000000000008484, 0x0000000021212121, 14 );
+ TEST_RR_OP( 16, srlw, 0x0000000000000000, 0x0000000021212121, 31 );
+
+ # Verify that shifts only use bottom five bits
+
+ TEST_RR_OP( 17, srlw, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffe0 );
+ TEST_RR_OP( 18, srlw, 0x0000000010909090, 0x0000000021212121, 0xffffffffffffffe1 );
+ TEST_RR_OP( 19, srlw, 0x0000000000424242, 0x0000000021212121, 0xffffffffffffffe7 );
+ TEST_RR_OP( 20, srlw, 0x0000000000008484, 0x0000000021212121, 0xffffffffffffffee );
+ TEST_RR_OP( 21, srlw, 0x0000000000000000, 0x0000000021212121, 0xffffffffffffffff );
+
+ # Verify that shifts ignore top 32 (using true 64-bit values)
+
+ TEST_RR_OP( 44, srlw, 0x0000000012345678, 0xffffffff12345678, 0 );
+ TEST_RR_OP( 45, srlw, 0x0000000001234567, 0xffffffff12345678, 4 );
+ TEST_RR_OP( 46, srlw, 0xffffffff92345678, 0x0000000092345678, 0 );
+ TEST_RR_OP( 47, srlw, 0x0000000009234567, 0x0000000092345678, 4 );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 22, srlw, 0x0000000001000000, 0xffffffff80000000, 7 );
+ TEST_RR_SRC2_EQ_DEST( 23, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
+ TEST_RR_SRC12_EQ_DEST( 24, srlw, 0, 7 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 25, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7 );
+ TEST_RR_DEST_BYPASS( 26, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
+ TEST_RR_DEST_BYPASS( 27, 2, srlw, 0x0000000000000001, 0xffffffff80000000, 31 );
+
+ TEST_RR_SRC12_BYPASS( 28, 0, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7 );
+ TEST_RR_SRC12_BYPASS( 29, 0, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
+ TEST_RR_SRC12_BYPASS( 30, 0, 2, srlw, 0x0000000000000001, 0xffffffff80000000, 31 );
+ TEST_RR_SRC12_BYPASS( 31, 1, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7 );
+ TEST_RR_SRC12_BYPASS( 32, 1, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
+ TEST_RR_SRC12_BYPASS( 33, 2, 0, srlw, 0x0000000000000001, 0xffffffff80000000, 31 );
+
+ TEST_RR_SRC21_BYPASS( 34, 0, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7 );
+ TEST_RR_SRC21_BYPASS( 35, 0, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
+ TEST_RR_SRC21_BYPASS( 36, 0, 2, srlw, 0x0000000000000001, 0xffffffff80000000, 31 );
+ TEST_RR_SRC21_BYPASS( 37, 1, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7 );
+ TEST_RR_SRC21_BYPASS( 38, 1, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
+ TEST_RR_SRC21_BYPASS( 39, 2, 0, srlw, 0x0000000000000001, 0xffffffff80000000, 31 );
+
+ TEST_RR_ZEROSRC1( 40, srlw, 0, 15 );
+ TEST_RR_ZEROSRC2( 41, srlw, 32, 32 );
+ TEST_RR_ZEROSRC12( 42, srlw, 0 );
+ TEST_RR_ZERODEST( 43, srlw, 1024, 2048 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/st_ld.S b/tests/riscv-tests/rv32ui/st_ld.S
@@ -0,0 +1,130 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# st_ld.S
+#-----------------------------------------------------------------------------
+#
+# Test store and load instructions
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Bypassing Tests
+ #-------------------------------------------------------------
+
+ # Test sb and lb (signed byte)
+ TEST_ST_LD_BYPASS(2, lb, sb, 0xffffffffffffffdd, 0, tdat );
+ TEST_ST_LD_BYPASS(3, lb, sb, 0xffffffffffffffcd, 1, tdat );
+ TEST_ST_LD_BYPASS(4, lb, sb, 0xffffffffffffffcc, 2, tdat );
+ TEST_ST_LD_BYPASS(5, lb, sb, 0xffffffffffffffbc, 3, tdat );
+ TEST_ST_LD_BYPASS(6, lb, sb, 0xffffffffffffffbb, 4, tdat );
+ TEST_ST_LD_BYPASS(7, lb, sb, 0xffffffffffffffab, 5, tdat );
+
+ TEST_ST_LD_BYPASS(8, lb, sb, 0x33, 0, tdat );
+ TEST_ST_LD_BYPASS(9, lb, sb, 0x23, 1, tdat );
+ TEST_ST_LD_BYPASS(10, lb, sb, 0x22, 2, tdat );
+ TEST_ST_LD_BYPASS(11, lb, sb, 0x12, 3, tdat );
+ TEST_ST_LD_BYPASS(12, lb, sb, 0x11, 4, tdat );
+ TEST_ST_LD_BYPASS(13, lb, sb, 0x01, 5, tdat );
+
+ # Test sb and lbu (unsigned byte)
+ TEST_ST_LD_BYPASS(14, lbu, sb, 0x33, 0, tdat );
+ TEST_ST_LD_BYPASS(15, lbu, sb, 0x23, 1, tdat );
+ TEST_ST_LD_BYPASS(16, lbu, sb, 0x22, 2, tdat );
+ TEST_ST_LD_BYPASS(17, lbu, sb, 0x12, 3, tdat );
+ TEST_ST_LD_BYPASS(18, lbu, sb, 0x11, 4, tdat );
+ TEST_ST_LD_BYPASS(19, lbu, sb, 0x01, 5, tdat );
+
+ # Test sw and lw (signed word)
+ TEST_ST_LD_BYPASS(20, lw, sw, 0xffffffffaabbccdd, 0, tdat );
+ TEST_ST_LD_BYPASS(21, lw, sw, 0xffffffffdaabbccd, 4, tdat );
+ TEST_ST_LD_BYPASS(22, lw, sw, 0xffffffffddaabbcc, 8, tdat );
+ TEST_ST_LD_BYPASS(23, lw, sw, 0xffffffffcddaabbc, 12, tdat );
+ TEST_ST_LD_BYPASS(24, lw, sw, 0xffffffffccddaabb, 16, tdat );
+ TEST_ST_LD_BYPASS(25, lw, sw, 0xffffffffbccddaab, 20, tdat );
+
+ TEST_ST_LD_BYPASS(26, lw, sw, 0x00112233, 0, tdat );
+ TEST_ST_LD_BYPASS(27, lw, sw, 0x30011223, 4, tdat );
+ TEST_ST_LD_BYPASS(28, lw, sw, 0x33001122, 8, tdat );
+ TEST_ST_LD_BYPASS(29, lw, sw, 0x23300112, 12, tdat );
+ TEST_ST_LD_BYPASS(30, lw, sw, 0x22330011, 16, tdat );
+ TEST_ST_LD_BYPASS(31, lw, sw, 0x12233001, 20, tdat );
+
+ # Test sh and lh (signed halfword)
+ TEST_ST_LD_BYPASS(32, lh, sh, 0xffffffffffffccdd, 0, tdat );
+ TEST_ST_LD_BYPASS(33, lh, sh, 0xffffffffffffbccd, 2, tdat );
+ TEST_ST_LD_BYPASS(34, lh, sh, 0xffffffffffffbbcc, 4, tdat );
+ TEST_ST_LD_BYPASS(35, lh, sh, 0xffffffffffffabbc, 6, tdat );
+ TEST_ST_LD_BYPASS(36, lh, sh, 0xffffffffffffaabb, 8, tdat );
+ TEST_ST_LD_BYPASS(37, lh, sh, 0xffffffffffffdaab, 10, tdat );
+
+ TEST_ST_LD_BYPASS(38, lh, sh, 0x2233, 0, tdat );
+ TEST_ST_LD_BYPASS(39, lh, sh, 0x1223, 2, tdat );
+ TEST_ST_LD_BYPASS(40, lh, sh, 0x1122, 4, tdat );
+ TEST_ST_LD_BYPASS(41, lh, sh, 0x0112, 6, tdat );
+ TEST_ST_LD_BYPASS(42, lh, sh, 0x0011, 8, tdat );
+ TEST_ST_LD_BYPASS(43, lh, sh, 0x3001, 10, tdat );
+
+ # Test sh and lhu (unsigned halfword)
+ TEST_ST_LD_BYPASS(44, lhu, sh, 0x2233, 0, tdat );
+ TEST_ST_LD_BYPASS(45, lhu, sh, 0x1223, 2, tdat );
+ TEST_ST_LD_BYPASS(46, lhu, sh, 0x1122, 4, tdat );
+ TEST_ST_LD_BYPASS(47, lhu, sh, 0x0112, 6, tdat );
+ TEST_ST_LD_BYPASS(48, lhu, sh, 0x0011, 8, tdat );
+ TEST_ST_LD_BYPASS(49, lhu, sh, 0x3001, 10, tdat );
+
+ # RV64-specific tests for ld, sd, and lwu
+#if __riscv_xlen == 64
+ # Test sd and ld (doubleword)
+ TEST_ST_LD_BYPASS(50, ld, sd, 0x0011223344556677, 0, tdat );
+ TEST_ST_LD_BYPASS(51, ld, sd, 0x1122334455667788, 8, tdat );
+ TEST_ST_LD_BYPASS(52, ld, sd, 0x2233445566778899, 16, tdat );
+ TEST_ST_LD_BYPASS(53, ld, sd, 0xabbccdd, 0, tdat );
+ TEST_ST_LD_BYPASS(54, ld, sd, 0xaabbccd, 8, tdat );
+ TEST_ST_LD_BYPASS(55, ld, sd, 0xdaabbcc, 16, tdat );
+ TEST_ST_LD_BYPASS(56, ld, sd, 0xddaabbc, 24, tdat );
+ TEST_ST_LD_BYPASS(57, ld, sd, 0xcddaabb, 32, tdat );
+ TEST_ST_LD_BYPASS(58, ld, sd, 0xccddaab, 40, tdat );
+
+ TEST_ST_LD_BYPASS(59, ld, sd, 0x00112233, 0, tdat );
+ TEST_ST_LD_BYPASS(60, ld, sd, 0x30011223, 8, tdat );
+ TEST_ST_LD_BYPASS(61, ld, sd, 0x33001122, 16, tdat );
+ TEST_ST_LD_BYPASS(62, ld, sd, 0x23300112, 24, tdat );
+ TEST_ST_LD_BYPASS(63, ld, sd, 0x22330011, 32, tdat );
+ TEST_ST_LD_BYPASS(64, ld, sd, 0x12233001, 40, tdat );
+
+ # Test sw and lwu (unsigned word)
+ TEST_ST_LD_BYPASS(65, lwu, sw, 0x00112233, 0, tdat );
+ TEST_ST_LD_BYPASS(66, lwu, sw, 0x33001122, 8, tdat );
+ TEST_ST_LD_BYPASS(67, lwu, sw, 0x30011223, 4, tdat );
+ TEST_ST_LD_BYPASS(68, lwu, sw, 0x23300112, 12, tdat );
+ TEST_ST_LD_BYPASS(69, lwu, sw, 0x22330011, 16, tdat );
+ TEST_ST_LD_BYPASS(70, lwu, sw, 0x12233001, 20, tdat );
+#endif
+
+ li a0, 0xef # Immediate load for manual store test
+ la a1, tdat # Load address of tdat
+ sb a0, 3(a1) # Store byte at offset 3 of tdat
+ lb a2, 3(a1) # Load byte back for verification
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+tdat:
+ .rept 20
+ .word 0xdeadbeef
+ .endr
+
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/sub.S b/tests/riscv-tests/rv32ui/sub.S
@@ -0,0 +1,83 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sub.S
+#-----------------------------------------------------------------------------
+#
+# Test sub instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, sub, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000 );
+ TEST_RR_OP( 3, sub, 0x0000000000000000, 0x0000000000000001, 0x0000000000000001 );
+ TEST_RR_OP( 4, sub, 0xfffffffffffffffc, 0x0000000000000003, 0x0000000000000007 );
+
+ TEST_RR_OP( 5, sub, 0x0000000000008000, 0x0000000000000000, 0xffffffffffff8000 );
+ TEST_RR_OP( 6, sub, 0xffffffff80000000, 0xffffffff80000000, 0x0000000000000000 );
+ TEST_RR_OP( 7, sub, 0xffffffff80008000, 0xffffffff80000000, 0xffffffffffff8000 );
+
+ TEST_RR_OP( 8, sub, 0xffffffffffff8001, 0x0000000000000000, 0x0000000000007fff );
+ TEST_RR_OP( 9, sub, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 );
+ TEST_RR_OP( 10, sub, 0x000000007fff8000, 0x000000007fffffff, 0x0000000000007fff );
+
+ TEST_RR_OP( 11, sub, 0xffffffff7fff8001, 0xffffffff80000000, 0x0000000000007fff );
+ TEST_RR_OP( 12, sub, 0x0000000080007fff, 0x000000007fffffff, 0xffffffffffff8000 );
+
+ TEST_RR_OP( 13, sub, 0x0000000000000001, 0x0000000000000000, 0xffffffffffffffff );
+ TEST_RR_OP( 14, sub, 0xfffffffffffffffe, 0xffffffffffffffff, 0x0000000000000001 );
+ TEST_RR_OP( 15, sub, 0x0000000000000000, 0xffffffffffffffff, 0xffffffffffffffff );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 16, sub, 2, 13, 11 );
+ TEST_RR_SRC2_EQ_DEST( 17, sub, 3, 14, 11 );
+ TEST_RR_SRC12_EQ_DEST( 18, sub, 0, 13 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 19, 0, sub, 2, 13, 11 );
+ TEST_RR_DEST_BYPASS( 20, 1, sub, 3, 14, 11 );
+ TEST_RR_DEST_BYPASS( 21, 2, sub, 4, 15, 11 );
+
+ TEST_RR_SRC12_BYPASS( 22, 0, 0, sub, 2, 13, 11 );
+ TEST_RR_SRC12_BYPASS( 23, 0, 1, sub, 3, 14, 11 );
+ TEST_RR_SRC12_BYPASS( 24, 0, 2, sub, 4, 15, 11 );
+ TEST_RR_SRC12_BYPASS( 25, 1, 0, sub, 2, 13, 11 );
+ TEST_RR_SRC12_BYPASS( 26, 1, 1, sub, 3, 14, 11 );
+ TEST_RR_SRC12_BYPASS( 27, 2, 0, sub, 4, 15, 11 );
+
+ TEST_RR_SRC21_BYPASS( 28, 0, 0, sub, 2, 13, 11 );
+ TEST_RR_SRC21_BYPASS( 29, 0, 1, sub, 3, 14, 11 );
+ TEST_RR_SRC21_BYPASS( 30, 0, 2, sub, 4, 15, 11 );
+ TEST_RR_SRC21_BYPASS( 31, 1, 0, sub, 2, 13, 11 );
+ TEST_RR_SRC21_BYPASS( 32, 1, 1, sub, 3, 14, 11 );
+ TEST_RR_SRC21_BYPASS( 33, 2, 0, sub, 4, 15, 11 );
+
+ TEST_RR_ZEROSRC1( 34, sub, 15, -15 );
+ TEST_RR_ZEROSRC2( 35, sub, 32, 32 );
+ TEST_RR_ZEROSRC12( 36, sub, 0 );
+ TEST_RR_ZERODEST( 37, sub, 16, 30 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/subw.S b/tests/riscv-tests/rv32ui/subw.S
@@ -0,0 +1,83 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# subw.S
+#-----------------------------------------------------------------------------
+#
+# Test subw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, subw, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000 );
+ TEST_RR_OP( 3, subw, 0x0000000000000000, 0x0000000000000001, 0x0000000000000001 );
+ TEST_RR_OP( 4, subw, 0xfffffffffffffffc, 0x0000000000000003, 0x0000000000000007 );
+
+ TEST_RR_OP( 5, subw, 0x0000000000008000, 0x0000000000000000, 0xffffffffffff8000 );
+ TEST_RR_OP( 6, subw, 0xffffffff80000000, 0xffffffff80000000, 0x0000000000000000 );
+ TEST_RR_OP( 7, subw, 0xffffffff80008000, 0xffffffff80000000, 0xffffffffffff8000 );
+
+ TEST_RR_OP( 8, subw, 0xffffffffffff8001, 0x0000000000000000, 0x0000000000007fff );
+ TEST_RR_OP( 9, subw, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 );
+ TEST_RR_OP( 10, subw, 0x000000007fff8000, 0x000000007fffffff, 0x0000000000007fff );
+
+ TEST_RR_OP( 11, subw, 0x000000007fff8001, 0xffffffff80000000, 0x0000000000007fff );
+ TEST_RR_OP( 12, subw, 0xffffffff80007fff, 0x000000007fffffff, 0xffffffffffff8000 );
+
+ TEST_RR_OP( 13, subw, 0x0000000000000001, 0x0000000000000000, 0xffffffffffffffff );
+ TEST_RR_OP( 14, subw, 0xfffffffffffffffe, 0xffffffffffffffff, 0x0000000000000001 );
+ TEST_RR_OP( 15, subw, 0x0000000000000000, 0xffffffffffffffff, 0xffffffffffffffff );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 16, subw, 2, 13, 11 );
+ TEST_RR_SRC2_EQ_DEST( 17, subw, 3, 14, 11 );
+ TEST_RR_SRC12_EQ_DEST( 18, subw, 0, 13 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 19, 0, subw, 2, 13, 11 );
+ TEST_RR_DEST_BYPASS( 20, 1, subw, 3, 14, 11 );
+ TEST_RR_DEST_BYPASS( 21, 2, subw, 4, 15, 11 );
+
+ TEST_RR_SRC12_BYPASS( 22, 0, 0, subw, 2, 13, 11 );
+ TEST_RR_SRC12_BYPASS( 23, 0, 1, subw, 3, 14, 11 );
+ TEST_RR_SRC12_BYPASS( 24, 0, 2, subw, 4, 15, 11 );
+ TEST_RR_SRC12_BYPASS( 25, 1, 0, subw, 2, 13, 11 );
+ TEST_RR_SRC12_BYPASS( 26, 1, 1, subw, 3, 14, 11 );
+ TEST_RR_SRC12_BYPASS( 27, 2, 0, subw, 4, 15, 11 );
+
+ TEST_RR_SRC21_BYPASS( 28, 0, 0, subw, 2, 13, 11 );
+ TEST_RR_SRC21_BYPASS( 29, 0, 1, subw, 3, 14, 11 );
+ TEST_RR_SRC21_BYPASS( 30, 0, 2, subw, 4, 15, 11 );
+ TEST_RR_SRC21_BYPASS( 31, 1, 0, subw, 2, 13, 11 );
+ TEST_RR_SRC21_BYPASS( 32, 1, 1, subw, 3, 14, 11 );
+ TEST_RR_SRC21_BYPASS( 33, 2, 0, subw, 4, 15, 11 );
+
+ TEST_RR_ZEROSRC1( 34, subw, 15, -15 );
+ TEST_RR_ZEROSRC2( 35, subw, 32, 32 );
+ TEST_RR_ZEROSRC12( 36, subw, 0 );
+ TEST_RR_ZERODEST( 37, subw, 16, 30 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/sw.S b/tests/riscv-tests/rv32ui/sw.S
@@ -0,0 +1,92 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sw.S
+#-----------------------------------------------------------------------------
+#
+# Test sw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Basic tests
+ #-------------------------------------------------------------
+
+ TEST_ST_OP( 2, lw, sw, 0x0000000000aa00aa, 0, tdat );
+ TEST_ST_OP( 3, lw, sw, 0xffffffffaa00aa00, 4, tdat );
+ TEST_ST_OP( 4, lw, sw, 0x000000000aa00aa0, 8, tdat );
+ TEST_ST_OP( 5, lw, sw, 0xffffffffa00aa00a, 12, tdat );
+
+ # Test with negative offset
+
+ TEST_ST_OP( 6, lw, sw, 0x0000000000aa00aa, -12, tdat8 );
+ TEST_ST_OP( 7, lw, sw, 0xffffffffaa00aa00, -8, tdat8 );
+ TEST_ST_OP( 8, lw, sw, 0x000000000aa00aa0, -4, tdat8 );
+ TEST_ST_OP( 9, lw, sw, 0xffffffffa00aa00a, 0, tdat8 );
+
+ # Test with a negative base
+
+ TEST_CASE( 10, x5, 0x12345678, \
+ la x1, tdat9; \
+ li x2, 0x12345678; \
+ addi x4, x1, -32; \
+ sw x2, 32(x4); \
+ lw x5, 0(x1); \
+ )
+
+ # Test with unaligned base
+
+ TEST_CASE( 11, x5, 0x58213098, \
+ la x1, tdat9; \
+ li x2, 0x58213098; \
+ addi x1, x1, -3; \
+ sw x2, 7(x1); \
+ la x4, tdat10; \
+ lw x5, 0(x4); \
+ )
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_ST_SRC12_BYPASS( 12, 0, 0, lw, sw, 0xffffffffaabbccdd, 0, tdat );
+ TEST_ST_SRC12_BYPASS( 13, 0, 1, lw, sw, 0xffffffffdaabbccd, 4, tdat );
+ TEST_ST_SRC12_BYPASS( 14, 0, 2, lw, sw, 0xffffffffddaabbcc, 8, tdat );
+ TEST_ST_SRC12_BYPASS( 15, 1, 0, lw, sw, 0xffffffffcddaabbc, 12, tdat );
+ TEST_ST_SRC12_BYPASS( 16, 1, 1, lw, sw, 0xffffffffccddaabb, 16, tdat );
+ TEST_ST_SRC12_BYPASS( 17, 2, 0, lw, sw, 0xffffffffbccddaab, 20, tdat );
+
+ TEST_ST_SRC21_BYPASS( 18, 0, 0, lw, sw, 0x00112233, 0, tdat );
+ TEST_ST_SRC21_BYPASS( 19, 0, 1, lw, sw, 0x30011223, 4, tdat );
+ TEST_ST_SRC21_BYPASS( 20, 0, 2, lw, sw, 0x33001122, 8, tdat );
+ TEST_ST_SRC21_BYPASS( 21, 1, 0, lw, sw, 0x23300112, 12, tdat );
+ TEST_ST_SRC21_BYPASS( 22, 1, 1, lw, sw, 0x22330011, 16, tdat );
+ TEST_ST_SRC21_BYPASS( 23, 2, 0, lw, sw, 0x12233001, 20, tdat );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+tdat:
+tdat1: .word 0xdeadbeef
+tdat2: .word 0xdeadbeef
+tdat3: .word 0xdeadbeef
+tdat4: .word 0xdeadbeef
+tdat5: .word 0xdeadbeef
+tdat6: .word 0xdeadbeef
+tdat7: .word 0xdeadbeef
+tdat8: .word 0xdeadbeef
+tdat9: .word 0xdeadbeef
+tdat10: .word 0xdeadbeef
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/xor.S b/tests/riscv-tests/rv32ui/xor.S
@@ -0,0 +1,69 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# xor.S
+#-----------------------------------------------------------------------------
+#
+# Test xor instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Logical tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_OP( 3, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
+ TEST_RR_OP( 4, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
+ TEST_RR_OP( 5, xor, 0x00ff00ff, 0xf00ff00f, 0xf0f0f0f0 );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 6, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_SRC2_EQ_DEST( 7, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_SRC12_EQ_DEST( 8, xor, 0x00000000, 0xff00ff00 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 9, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_DEST_BYPASS( 10, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
+ TEST_RR_DEST_BYPASS( 11, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
+
+ TEST_RR_SRC12_BYPASS( 12, 0, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_SRC12_BYPASS( 13, 0, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
+ TEST_RR_SRC12_BYPASS( 14, 0, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
+ TEST_RR_SRC12_BYPASS( 15, 1, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_SRC12_BYPASS( 16, 1, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
+ TEST_RR_SRC12_BYPASS( 17, 2, 0, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
+
+ TEST_RR_SRC21_BYPASS( 18, 0, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_SRC21_BYPASS( 19, 0, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
+ TEST_RR_SRC21_BYPASS( 20, 0, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
+ TEST_RR_SRC21_BYPASS( 21, 1, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_SRC21_BYPASS( 22, 1, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
+ TEST_RR_SRC21_BYPASS( 23, 2, 0, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
+
+ TEST_RR_ZEROSRC1( 24, xor, 0xff00ff00, 0xff00ff00 );
+ TEST_RR_ZEROSRC2( 25, xor, 0x00ff00ff, 0x00ff00ff );
+ TEST_RR_ZEROSRC12( 26, xor, 0 );
+ TEST_RR_ZERODEST( 27, xor, 0x11111111, 0x22222222 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32ui/xori.S b/tests/riscv-tests/rv32ui/xori.S
@@ -0,0 +1,55 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# xori.S
+#-----------------------------------------------------------------------------
+#
+# Test xori instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Logical tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_OP( 2, xori, 0xffffffffff00f00f, 0x0000000000ff0f00, 0xf0f );
+ TEST_IMM_OP( 3, xori, 0x000000000ff00f00, 0x000000000ff00ff0, 0x0f0 );
+ TEST_IMM_OP( 4, xori, 0x0000000000ff0ff0, 0x0000000000ff08ff, 0x70f );
+ TEST_IMM_OP( 5, xori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_SRC1_EQ_DEST( 6, xori, 0xffffffffff00f00f, 0xffffffffff00f700, 0x70f );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_DEST_BYPASS( 7, 0, xori, 0x000000000ff00f00, 0x000000000ff00ff0, 0x0f0 );
+ TEST_IMM_DEST_BYPASS( 8, 1, xori, 0x0000000000ff0ff0, 0x0000000000ff08ff, 0x70f );
+ TEST_IMM_DEST_BYPASS( 9, 2, xori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 );
+
+ TEST_IMM_SRC1_BYPASS( 10, 0, xori, 0x000000000ff00f00, 0x000000000ff00ff0, 0x0f0 );
+ TEST_IMM_SRC1_BYPASS( 11, 1, xori, 0x0000000000ff0ff0, 0x0000000000ff0fff, 0x00f );
+ TEST_IMM_SRC1_BYPASS( 12, 2, xori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 );
+
+ TEST_IMM_ZEROSRC1( 13, xori, 0x0f0, 0x0f0 );
+ TEST_IMM_ZERODEST( 14, xori, 0x00ff00ff, 0x70f );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32um/div.S b/tests/riscv-tests/rv32um/div.S
@@ -0,0 +1,41 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# div.S
+#-----------------------------------------------------------------------------
+#
+# Test div instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, div, 3, 20, 6 );
+ TEST_RR_OP( 3, div, -3, -20, 6 );
+ TEST_RR_OP( 4, div, -3, 20, -6 );
+ TEST_RR_OP( 5, div, 3, -20, -6 );
+
+ TEST_RR_OP( 6, div, -1<<31, -1<<31, 1 );
+ TEST_RR_OP( 7, div, -1<<31, -1<<31, -1 );
+
+ TEST_RR_OP( 8, div, -1, -1<<31, 0 );
+ TEST_RR_OP( 9, div, -1, 1, 0 );
+ TEST_RR_OP(10, div, -1, 0, 0 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32um/divu.S b/tests/riscv-tests/rv32um/divu.S
@@ -0,0 +1,41 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# divu.S
+#-----------------------------------------------------------------------------
+#
+# Test divu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, divu, 3, 20, 6 );
+ TEST_RR_OP( 3, divu, 715827879, -20, 6 );
+ TEST_RR_OP( 4, divu, 0, 20, -6 );
+ TEST_RR_OP( 5, divu, 0, -20, -6 );
+
+ TEST_RR_OP( 6, divu, -1<<31, -1<<31, 1 );
+ TEST_RR_OP( 7, divu, 0, -1<<31, -1 );
+
+ TEST_RR_OP( 8, divu, -1, -1<<31, 0 );
+ TEST_RR_OP( 9, divu, -1, 1, 0 );
+ TEST_RR_OP(10, divu, -1, 0, 0 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32um/mul.S b/tests/riscv-tests/rv32um/mul.S
@@ -0,0 +1,84 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# mul.S
+#-----------------------------------------------------------------------------
+#
+# Test mul instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP(32, mul, 0x00001200, 0x00007e00, 0xb6db6db7 );
+ TEST_RR_OP(33, mul, 0x00001240, 0x00007fc0, 0xb6db6db7 );
+
+ TEST_RR_OP( 2, mul, 0x00000000, 0x00000000, 0x00000000 );
+ TEST_RR_OP( 3, mul, 0x00000001, 0x00000001, 0x00000001 );
+ TEST_RR_OP( 4, mul, 0x00000015, 0x00000003, 0x00000007 );
+
+ TEST_RR_OP( 5, mul, 0x00000000, 0x00000000, 0xffff8000 );
+ TEST_RR_OP( 6, mul, 0x00000000, 0x80000000, 0x00000000 );
+ TEST_RR_OP( 7, mul, 0x00000000, 0x80000000, 0xffff8000 );
+
+ TEST_RR_OP(30, mul, 0x0000ff7f, 0xaaaaaaab, 0x0002fe7d );
+ TEST_RR_OP(31, mul, 0x0000ff7f, 0x0002fe7d, 0xaaaaaaab );
+
+ TEST_RR_OP(34, mul, 0x00000000, 0xff000000, 0xff000000 );
+
+ TEST_RR_OP(35, mul, 0x00000001, 0xffffffff, 0xffffffff );
+ TEST_RR_OP(36, mul, 0xffffffff, 0xffffffff, 0x00000001 );
+ TEST_RR_OP(37, mul, 0xffffffff, 0x00000001, 0xffffffff );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 8, mul, 143, 13, 11 );
+ TEST_RR_SRC2_EQ_DEST( 9, mul, 154, 14, 11 );
+ TEST_RR_SRC12_EQ_DEST( 10, mul, 169, 13 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 11, 0, mul, 143, 13, 11 );
+ TEST_RR_DEST_BYPASS( 12, 1, mul, 154, 14, 11 );
+ TEST_RR_DEST_BYPASS( 13, 2, mul, 165, 15, 11 );
+
+ TEST_RR_SRC12_BYPASS( 14, 0, 0, mul, 143, 13, 11 );
+ TEST_RR_SRC12_BYPASS( 15, 0, 1, mul, 154, 14, 11 );
+ TEST_RR_SRC12_BYPASS( 16, 0, 2, mul, 165, 15, 11 );
+ TEST_RR_SRC12_BYPASS( 17, 1, 0, mul, 143, 13, 11 );
+ TEST_RR_SRC12_BYPASS( 18, 1, 1, mul, 154, 14, 11 );
+ TEST_RR_SRC12_BYPASS( 19, 2, 0, mul, 165, 15, 11 );
+
+ TEST_RR_SRC21_BYPASS( 20, 0, 0, mul, 143, 13, 11 );
+ TEST_RR_SRC21_BYPASS( 21, 0, 1, mul, 154, 14, 11 );
+ TEST_RR_SRC21_BYPASS( 22, 0, 2, mul, 165, 15, 11 );
+ TEST_RR_SRC21_BYPASS( 23, 1, 0, mul, 143, 13, 11 );
+ TEST_RR_SRC21_BYPASS( 24, 1, 1, mul, 154, 14, 11 );
+ TEST_RR_SRC21_BYPASS( 25, 2, 0, mul, 165, 15, 11 );
+
+ TEST_RR_ZEROSRC1( 26, mul, 0, 31 );
+ TEST_RR_ZEROSRC2( 27, mul, 0, 32 );
+ TEST_RR_ZEROSRC12( 28, mul, 0 );
+ TEST_RR_ZERODEST( 29, mul, 33, 34 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32um/mulh.S b/tests/riscv-tests/rv32um/mulh.S
@@ -0,0 +1,81 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# mulh.S
+#-----------------------------------------------------------------------------
+#
+# Test mulh instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, mulh, 0x00000000, 0x00000000, 0x00000000 );
+ TEST_RR_OP( 3, mulh, 0x00000000, 0x00000001, 0x00000001 );
+ TEST_RR_OP( 4, mulh, 0x00000000, 0x00000003, 0x00000007 );
+
+ TEST_RR_OP( 5, mulh, 0x00000000, 0x00000000, 0xffff8000 );
+ TEST_RR_OP( 6, mulh, 0x00000000, 0x80000000, 0x00000000 );
+ TEST_RR_OP( 7, mulh, 0x00004000, 0x80000000, 0xffff8000 );
+
+ TEST_RR_OP(30, mulh, 0xffff0081, 0xaaaaaaab, 0x0002fe7d );
+ TEST_RR_OP(31, mulh, 0xffff0081, 0x0002fe7d, 0xaaaaaaab );
+
+ TEST_RR_OP(32, mulh, 0x00010000, 0xff000000, 0xff000000 );
+
+ TEST_RR_OP(33, mulh, 0x00000000, 0xffffffff, 0xffffffff );
+ TEST_RR_OP(34, mulh, 0xffffffff, 0xffffffff, 0x00000001 );
+ TEST_RR_OP(35, mulh, 0xffffffff, 0x00000001, 0xffffffff );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 8, mulh, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC2_EQ_DEST( 9, mulh, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC12_EQ_DEST( 10, mulh, 43264, 13<<20 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 11, 0, mulh, 36608, 13<<20, 11<<20 );
+ TEST_RR_DEST_BYPASS( 12, 1, mulh, 39424, 14<<20, 11<<20 );
+ TEST_RR_DEST_BYPASS( 13, 2, mulh, 42240, 15<<20, 11<<20 );
+
+ TEST_RR_SRC12_BYPASS( 14, 0, 0, mulh, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 15, 0, 1, mulh, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 16, 0, 2, mulh, 42240, 15<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 17, 1, 0, mulh, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 18, 1, 1, mulh, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 19, 2, 0, mulh, 42240, 15<<20, 11<<20 );
+
+ TEST_RR_SRC21_BYPASS( 20, 0, 0, mulh, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 21, 0, 1, mulh, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 22, 0, 2, mulh, 42240, 15<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 23, 1, 0, mulh, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 24, 1, 1, mulh, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 25, 2, 0, mulh, 42240, 15<<20, 11<<20 );
+
+ TEST_RR_ZEROSRC1( 26, mulh, 0, 31<<26 );
+ TEST_RR_ZEROSRC2( 27, mulh, 0, 32<<26 );
+ TEST_RR_ZEROSRC12( 28, mulh, 0 );
+ TEST_RR_ZERODEST( 29, mulh, 33<<20, 34<<20 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32um/mulhsu.S b/tests/riscv-tests/rv32um/mulhsu.S
@@ -0,0 +1,83 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# mulhsu.S
+#-----------------------------------------------------------------------------
+#
+# Test mulhsu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, mulhsu, 0x00000000, 0x00000000, 0x00000000 );
+ TEST_RR_OP( 3, mulhsu, 0x00000000, 0x00000001, 0x00000001 );
+ TEST_RR_OP( 4, mulhsu, 0x00000000, 0x00000003, 0x00000007 );
+
+ TEST_RR_OP( 5, mulhsu, 0x00000000, 0x00000000, 0xffff8000 );
+ TEST_RR_OP( 6, mulhsu, 0x00000000, 0x80000000, 0x00000000 );
+ TEST_RR_OP( 7, mulhsu, 0x80004000, 0x80000000, 0xffff8000 );
+
+ TEST_RR_OP(30, mulhsu, 0xffff0081, 0xaaaaaaab, 0x0002fe7d );
+ TEST_RR_OP(31, mulhsu, 0x0001fefe, 0x0002fe7d, 0xaaaaaaab );
+
+ TEST_RR_OP(32, mulhsu, 0xff010000, 0xff000000, 0xff000000 );
+
+ TEST_RR_OP(33, mulhsu, 0xffffffff, 0xffffffff, 0xffffffff );
+ TEST_RR_OP(34, mulhsu, 0xffffffff, 0xffffffff, 0x00000001 );
+ TEST_RR_OP(35, mulhsu, 0x00000000, 0x00000001, 0xffffffff );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 8, mulhsu, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC2_EQ_DEST( 9, mulhsu, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC12_EQ_DEST( 10, mulhsu, 43264, 13<<20 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 11, 0, mulhsu, 36608, 13<<20, 11<<20 );
+ TEST_RR_DEST_BYPASS( 12, 1, mulhsu, 39424, 14<<20, 11<<20 );
+ TEST_RR_DEST_BYPASS( 13, 2, mulhsu, 42240, 15<<20, 11<<20 );
+
+ TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhsu, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhsu, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhsu, 42240, 15<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhsu, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhsu, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhsu, 42240, 15<<20, 11<<20 );
+
+ TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhsu, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhsu, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhsu, 42240, 15<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhsu, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhsu, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhsu, 42240, 15<<20, 11<<20 );
+
+ TEST_RR_ZEROSRC1( 26, mulhsu, 0, 31<<26 );
+ TEST_RR_ZEROSRC2( 27, mulhsu, 0, 32<<26 );
+ TEST_RR_ZEROSRC12( 28, mulhsu, 0 );
+ TEST_RR_ZERODEST( 29, mulhsu, 33<<20, 34<<20 );
+
+
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32um/mulhu.S b/tests/riscv-tests/rv32um/mulhu.S
@@ -0,0 +1,82 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# mulhu.S
+#-----------------------------------------------------------------------------
+#
+# Test mulhu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, mulhu, 0x00000000, 0x00000000, 0x00000000 );
+ TEST_RR_OP( 3, mulhu, 0x00000000, 0x00000001, 0x00000001 );
+ TEST_RR_OP( 4, mulhu, 0x00000000, 0x00000003, 0x00000007 );
+
+ TEST_RR_OP( 5, mulhu, 0x00000000, 0x00000000, 0xffff8000 );
+ TEST_RR_OP( 6, mulhu, 0x00000000, 0x80000000, 0x00000000 );
+ TEST_RR_OP( 7, mulhu, 0x7fffc000, 0x80000000, 0xffff8000 );
+
+ TEST_RR_OP(30, mulhu, 0x0001fefe, 0xaaaaaaab, 0x0002fe7d );
+ TEST_RR_OP(31, mulhu, 0x0001fefe, 0x0002fe7d, 0xaaaaaaab );
+
+ TEST_RR_OP(32, mulhu, 0xfe010000, 0xff000000, 0xff000000 );
+
+ TEST_RR_OP(33, mulhu, 0xfffffffe, 0xffffffff, 0xffffffff );
+ TEST_RR_OP(34, mulhu, 0x00000000, 0xffffffff, 0x00000001 );
+ TEST_RR_OP(35, mulhu, 0x00000000, 0x00000001, 0xffffffff );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 8, mulhu, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC2_EQ_DEST( 9, mulhu, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC12_EQ_DEST( 10, mulhu, 43264, 13<<20 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 11, 0, mulhu, 36608, 13<<20, 11<<20 );
+ TEST_RR_DEST_BYPASS( 12, 1, mulhu, 39424, 14<<20, 11<<20 );
+ TEST_RR_DEST_BYPASS( 13, 2, mulhu, 42240, 15<<20, 11<<20 );
+
+ TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhu, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhu, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhu, 42240, 15<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhu, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhu, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhu, 42240, 15<<20, 11<<20 );
+
+ TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhu, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhu, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhu, 42240, 15<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhu, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhu, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhu, 42240, 15<<20, 11<<20 );
+
+ TEST_RR_ZEROSRC1( 26, mulhu, 0, 31<<26 );
+ TEST_RR_ZEROSRC2( 27, mulhu, 0, 32<<26 );
+ TEST_RR_ZEROSRC12( 28, mulhu, 0 );
+ TEST_RR_ZERODEST( 29, mulhu, 33<<20, 34<<20 );
+
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32um/rem.S b/tests/riscv-tests/rv32um/rem.S
@@ -0,0 +1,41 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# rem.S
+#-----------------------------------------------------------------------------
+#
+# Test rem instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, rem, 2, 20, 6 );
+ TEST_RR_OP( 3, rem, -2, -20, 6 );
+ TEST_RR_OP( 4, rem, 2, 20, -6 );
+ TEST_RR_OP( 5, rem, -2, -20, -6 );
+
+ TEST_RR_OP( 6, rem, 0, -1<<31, 1 );
+ TEST_RR_OP( 7, rem, 0, -1<<31, -1 );
+
+ TEST_RR_OP( 8, rem, -1<<31, -1<<31, 0 );
+ TEST_RR_OP( 9, rem, 1, 1, 0 );
+ TEST_RR_OP(10, rem, 0, 0, 0 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/rv32um/remu.S b/tests/riscv-tests/rv32um/remu.S
@@ -0,0 +1,41 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# remu.S
+#-----------------------------------------------------------------------------
+#
+# Test remu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, remu, 2, 20, 6 );
+ TEST_RR_OP( 3, remu, 2, -20, 6 );
+ TEST_RR_OP( 4, remu, 20, 20, -6 );
+ TEST_RR_OP( 5, remu, -20, -20, -6 );
+
+ TEST_RR_OP( 6, remu, 0, -1<<31, 1 );
+ TEST_RR_OP( 7, remu, -1<<31, -1<<31, -1 );
+
+ TEST_RR_OP( 8, remu, -1<<31, -1<<31, 0 );
+ TEST_RR_OP( 9, remu, 1, 1, 0 );
+ TEST_RR_OP(10, remu, 0, 0, 0 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/tests/riscv-tests/test_macros.h b/tests/riscv-tests/test_macros.h
@@ -0,0 +1,896 @@
+// See LICENSE for license details.
+
+#ifndef __TEST_MACROS_SCALAR_H
+#define __TEST_MACROS_SCALAR_H
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+
+#define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1))
+
+#define TEST_CASE( testnum, testreg, correctval, code... ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ code; \
+ li x7, MASK_XLEN(correctval); \
+ bne testreg, x7, fail;
+
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+
+#define TEST_INSERT_NOPS_0
+#define TEST_INSERT_NOPS_1 nop; TEST_INSERT_NOPS_0
+#define TEST_INSERT_NOPS_2 nop; TEST_INSERT_NOPS_1
+#define TEST_INSERT_NOPS_3 nop; TEST_INSERT_NOPS_2
+#define TEST_INSERT_NOPS_4 nop; TEST_INSERT_NOPS_3
+#define TEST_INSERT_NOPS_5 nop; TEST_INSERT_NOPS_4
+#define TEST_INSERT_NOPS_6 nop; TEST_INSERT_NOPS_5
+#define TEST_INSERT_NOPS_7 nop; TEST_INSERT_NOPS_6
+#define TEST_INSERT_NOPS_8 nop; TEST_INSERT_NOPS_7
+#define TEST_INSERT_NOPS_9 nop; TEST_INSERT_NOPS_8
+#define TEST_INSERT_NOPS_10 nop; TEST_INSERT_NOPS_9
+
+#if __riscv_xlen == 64
+#define LOAD_PTR ld
+#define STORE_PTR sd
+#else
+#define LOAD_PTR lw
+#define STORE_PTR sw
+#endif
+
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+
+#define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11))
+
+#define TEST_IMM_OP( testnum, inst, result, val1, imm ) \
+ TEST_CASE( testnum, x14, result, \
+ li x13, MASK_XLEN(val1); \
+ inst x14, x13, SEXT_IMM(imm); \
+ )
+
+#define TEST_IMM_OP_VXSAT( testnum, inst, result, val1, imm, expected_vxsat ) \
+ TEST_CASE( testnum, x14, result, \
+ TEST_VXSAT_CLEAR; \
+ li x13, MASK_XLEN(val1); \
+ inst x14, x13, SEXT_IMM(imm); \
+ ) \
+ TEST_VXSAT_CHECK( expected_vxsat )
+
+# RV32 P-extension register-pair immediate-op tests.
+# rs1 pair = {x13, x12} (even base), rd pair = {x15, x14}.
+# Both halves of result are checked; on mismatch we jump to the same fail
+# label as TEST_CASE, so the reported testnum matches.
+#define TEST_IMM_OP_PAIR( testnum, inst, result, val1, imm ) \
+ TEST_CASE( testnum, x14, ((result) & 0xFFFFFFFF), \
+ li x12, ((val1) & 0xFFFFFFFF); \
+ li x13, (((val1) >> 32) & 0xFFFFFFFF); \
+ inst x14, x12, SEXT_IMM(imm); \
+ ) \
+ li x7, (((result) >> 32) & 0xFFFFFFFF); \
+ bne x15, x7, fail;
+
+#define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \
+ TEST_CASE( testnum, x11, result, \
+ li x11, MASK_XLEN(val1); \
+ inst x11, x11, SEXT_IMM(imm); \
+ )
+
+#define TEST_IMM_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
+ TEST_CASE( testnum, x6, result, \
+ li x4, 0; \
+1: li x1, MASK_XLEN(val1); \
+ inst x14, x1, SEXT_IMM(imm); \
+ TEST_INSERT_NOPS_ ## nop_cycles \
+ addi x6, x14, 0; \
+ addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+ )
+
+#define TEST_IMM_SRC1_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
+ TEST_CASE( testnum, x14, result, \
+ li x4, 0; \
+1: li x1, MASK_XLEN(val1); \
+ TEST_INSERT_NOPS_ ## nop_cycles \
+ inst x14, x1, SEXT_IMM(imm); \
+ addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+ )
+
+#define TEST_IMM_ZEROSRC1( testnum, inst, result, imm ) \
+ TEST_CASE( testnum, x1, result, \
+ inst x1, x0, SEXT_IMM(imm); \
+ )
+
+#define TEST_IMM_ZERODEST( testnum, inst, val1, imm ) \
+ TEST_CASE( testnum, x0, 0, \
+ li x1, MASK_XLEN(val1); \
+ inst x0, x1, SEXT_IMM(imm); \
+ )
+
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+
+#define TEST_R_OP( testnum, inst, result, val1 ) \
+ TEST_CASE( testnum, x14, result, \
+ li x1, val1; \
+ inst x14, x1; \
+ )
+
+# P-extension vxsat helpers.
+# vxsat is a sticky CSR (0x009): set to 1 whenever an instruction saturates,
+# never auto-cleared. To verify it deterministically per test we clear it
+# before the instruction and check the expected post-value after.
+# Using the literal CSR address keeps these macros toolchain-independent.
+#define VXSAT_CSR 0x009
+#define TEST_VXSAT_CLEAR csrwi VXSAT_CSR, 0
+#define TEST_VXSAT_CHECK( expected_vxsat ) \
+ csrr x6, VXSAT_CSR; \
+ li x7, (expected_vxsat); \
+ bne x6, x7, fail;
+
+#define TEST_R_OP_VXSAT( testnum, inst, result, val1, expected_vxsat ) \
+ TEST_CASE( testnum, x14, result, \
+ TEST_VXSAT_CLEAR; \
+ li x1, val1; \
+ inst x14, x1; \
+ ) \
+ TEST_VXSAT_CHECK( expected_vxsat )
+
+#define TEST_R_SRC1_EQ_DEST( testnum, inst, result, val1 ) \
+ TEST_CASE( testnum, x1, result, \
+ li x1, val1; \
+ inst x1, x1; \
+ )
+
+#define TEST_R_DEST_BYPASS( testnum, nop_cycles, inst, result, val1 ) \
+ TEST_CASE( testnum, x6, result, \
+ li x4, 0; \
+1: li x1, val1; \
+ inst x14, x1; \
+ TEST_INSERT_NOPS_ ## nop_cycles \
+ addi x6, x14, 0; \
+ addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+ )
+
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+
+#define TEST_RR_OP( testnum, inst, result, val1, val2 ) \
+ TEST_CASE( testnum, x14, result, \
+ li x11, MASK_XLEN(val1); \
+ li x12, MASK_XLEN(val2); \
+ inst x14, x11, x12; \
+ )
+
+#define TEST_RR_OP_VXSAT( testnum, inst, result, val1, val2, expected_vxsat ) \
+ TEST_CASE( testnum, x14, result, \
+ TEST_VXSAT_CLEAR; \
+ li x11, MASK_XLEN(val1); \
+ li x12, MASK_XLEN(val2); \
+ inst x14, x11, x12; \
+ ) \
+ TEST_VXSAT_CHECK( expected_vxsat )
+
+# RV32 P-extension register-pair register-register tests.
+# rs1 pair = {x13, x12} (even base), rd pair = {x15, x14}, rs2 = x11.
+# Both halves of result are checked; on mismatch we jump to the same fail
+# label as TEST_CASE, so the reported testnum matches.
+#define TEST_RR_OP_PAIR( testnum, inst, result, val1, val2 ) \
+ TEST_CASE( testnum, x14, ((result) & 0xFFFFFFFF), \
+ li x12, ((val1) & 0xFFFFFFFF); \
+ li x13, (((val1) >> 32) & 0xFFFFFFFF); \
+ li x11, MASK_XLEN(val2); \
+ inst x14, x12, x11; \
+ ) \
+ li x7, (((result) >> 32) & 0xFFFFFFFF); \
+ bne x15, x7, fail;
+
+#define TEST_RR_SRC1_EQ_DEST( testnum, inst, result, val1, val2 ) \
+ TEST_CASE( testnum, x11, result, \
+ li x11, MASK_XLEN(val1); \
+ li x12, MASK_XLEN(val2); \
+ inst x11, x11, x12; \
+ )
+
+#define TEST_RR_SRC2_EQ_DEST( testnum, inst, result, val1, val2 ) \
+ TEST_CASE( testnum, x12, result, \
+ li x11, MASK_XLEN(val1); \
+ li x12, MASK_XLEN(val2); \
+ inst x12, x11, x12; \
+ )
+
+#define TEST_RR_SRC12_EQ_DEST( testnum, inst, result, val1 ) \
+ TEST_CASE( testnum, x11, result, \
+ li x11, MASK_XLEN(val1); \
+ inst x11, x11, x11; \
+ )
+
+#define TEST_RR_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, val2 ) \
+ TEST_CASE( testnum, x6, result, \
+ li x4, 0; \
+1: li x1, MASK_XLEN(val1); \
+ li x2, MASK_XLEN(val2); \
+ inst x14, x1, x2; \
+ TEST_INSERT_NOPS_ ## nop_cycles \
+ addi x6, x14, 0; \
+ addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+ )
+
+#define TEST_RR_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
+ TEST_CASE( testnum, x14, result, \
+ li x4, 0; \
+1: li x1, MASK_XLEN(val1); \
+ TEST_INSERT_NOPS_ ## src1_nops \
+ li x2, MASK_XLEN(val2); \
+ TEST_INSERT_NOPS_ ## src2_nops \
+ inst x14, x1, x2; \
+ addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+ )
+
+#define TEST_RR_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
+ TEST_CASE( testnum, x14, result, \
+ li x4, 0; \
+1: li x2, MASK_XLEN(val2); \
+ TEST_INSERT_NOPS_ ## src1_nops \
+ li x1, MASK_XLEN(val1); \
+ TEST_INSERT_NOPS_ ## src2_nops \
+ inst x14, x1, x2; \
+ addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+ )
+
+#define TEST_RR_ZEROSRC1( testnum, inst, result, val ) \
+ TEST_CASE( testnum, x2, result, \
+ li x1, MASK_XLEN(val); \
+ inst x2, x0, x1; \
+ )
+
+#define TEST_RR_ZEROSRC2( testnum, inst, result, val ) \
+ TEST_CASE( testnum, x2, result, \
+ li x1, MASK_XLEN(val); \
+ inst x2, x1, x0; \
+ )
+
+#define TEST_RR_ZEROSRC12( testnum, inst, result ) \
+ TEST_CASE( testnum, x1, result, \
+ inst x1, x0, x0; \
+ )
+
+#define TEST_RR_ZERODEST( testnum, inst, val1, val2 ) \
+ TEST_CASE( testnum, x0, 0, \
+ li x1, MASK_XLEN(val1); \
+ li x2, MASK_XLEN(val2); \
+ inst x0, x1, x2; \
+ )
+
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+
+#define TEST_LD_OP( testnum, inst, result, offset, base ) \
+ TEST_CASE( testnum, x14, result, \
+ li x15, result; /* Tell the exception handler the expected result. */ \
+ la x2, base; \
+ inst x14, offset(x2); \
+ )
+
+#define TEST_ST_OP( testnum, load_inst, store_inst, result, offset, base ) \
+ TEST_CASE( testnum, x14, result, \
+ la x2, base; \
+ li x1, result; \
+ la x15, 7f; /* Tell the exception handler how to skip this test. */ \
+ store_inst x1, offset(x2); \
+ load_inst x14, offset(x2); \
+ j 8f; \
+7: \
+ /* Set up the correct result for TEST_CASE(). */ \
+ mv x14, x1; \
+8: \
+ )
+
+#define TEST_LD_DEST_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ li x4, 0; \
+1: la x13, base; \
+ inst x14, offset(x13); \
+ TEST_INSERT_NOPS_ ## nop_cycles \
+ addi x6, x14, 0; \
+ li x7, result; \
+ bne x6, x7, fail; \
+ addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b; \
+
+#define TEST_LD_SRC1_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ li x4, 0; \
+1: la x13, base; \
+ TEST_INSERT_NOPS_ ## nop_cycles \
+ inst x14, offset(x13); \
+ li x7, result; \
+ bne x14, x7, fail; \
+ addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+
+#define TEST_ST_SRC12_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ li x4, 0; \
+1: li x13, result; \
+ TEST_INSERT_NOPS_ ## src1_nops \
+ la x12, base; \
+ TEST_INSERT_NOPS_ ## src2_nops \
+ store_inst x13, offset(x12); \
+ load_inst x14, offset(x12); \
+ li x7, result; \
+ bne x14, x7, fail; \
+ addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+
+#define TEST_ST_SRC21_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ li x4, 0; \
+1: la x2, base; \
+ TEST_INSERT_NOPS_ ## src1_nops \
+ li x1, result; \
+ TEST_INSERT_NOPS_ ## src2_nops \
+ store_inst x1, offset(x2); \
+ load_inst x14, offset(x2); \
+ li x7, result; \
+ bne x14, x7, fail; \
+ addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+
+#define TEST_LD_ST_BYPASS(testnum, load_inst, store_inst, result, offset, base) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ la x2, base; \
+ li x1, result; \
+ store_inst x1, offset(x2); \
+ load_inst x14, offset(x2); \
+ store_inst x14, offset(x2); \
+ load_inst x2, offset(x2); \
+ li x7, result; \
+ bne x2, x7, fail; \
+ la x2, base; \
+ STORE_PTR x2,8(x2); \
+ LOAD_PTR x4,8(x2); \
+ store_inst x1, offset(x4); \
+ bne x4, x2, fail; \
+ load_inst x14, offset(x4); \
+ bne x14, x7, fail; \
+
+#define TEST_ST_LD_BYPASS(testnum, load_inst, store_inst, result, offset, base) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ la x2, base; \
+ li x1, result; \
+ store_inst x1, offset(x2); \
+ load_inst x14, offset(x2); \
+ li x7, result; \
+ bne x14, x7, fail; \
+
+#define TEST_BR2_OP_TAKEN(testnum, inst, val1, val2 ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ li x1, val1; \
+ li x2, val2; \
+ inst x1, x2, 2f; \
+ bne x0, TESTNUM, fail; \
+1: bne x0, TESTNUM, 3f; \
+2: inst x1, x2, 1b; \
+ bne x0, TESTNUM, fail; \
+3:
+
+#define TEST_BR2_OP_NOTTAKEN( testnum, inst, val1, val2 ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ li x1, val1; \
+ li x2, val2; \
+ inst x1, x2, 1f; \
+ bne x0, TESTNUM, 2f; \
+1: bne x0, TESTNUM, fail; \
+2: inst x1, x2, 1b; \
+3:
+
+#define TEST_BR2_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ li x4, 0; \
+1: li x1, val1; \
+ TEST_INSERT_NOPS_ ## src1_nops \
+ li x2, val2; \
+ TEST_INSERT_NOPS_ ## src2_nops \
+ inst x1, x2, fail; \
+ addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+
+#define TEST_BR2_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ li x4, 0; \
+1: li x2, val2; \
+ TEST_INSERT_NOPS_ ## src1_nops \
+ li x1, val1; \
+ TEST_INSERT_NOPS_ ## src2_nops \
+ inst x1, x2, fail; \
+ addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+
+#define TEST_JR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ li x4, 0; \
+1: la x6, 2f; \
+ TEST_INSERT_NOPS_ ## nop_cycles \
+ inst x6; \
+ bne x0, TESTNUM, fail; \
+2: addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+
+#define TEST_JALR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ li x4, 0; \
+1: la x6, 2f; \
+ TEST_INSERT_NOPS_ ## nop_cycles \
+ inst x13, x6, 0; \
+ bne x0, TESTNUM, fail; \
+2: addi x4, x4, 1; \
+ li x5, 2; \
+ bne x4, x5, 1b \
+
+
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+
+# 16-bit half precision (float16)
+#define qNaNh 0x7e00
+#define sNaNh 0x7c01
+#define Infh 0x7c00
+#define nInfh 0xfc00
+
+# 32-bit single precision (float)
+#define qNaNf 0x7fc00000
+#define sNaNf 0x7f800001
+#define Inff 0x7f800000
+#define nInff 0xff800000
+
+# 64-bit double precision (double)
+#define qNaNd 0x7ff8000000000000
+#define sNaNd 0x7ff0000000000001
+#define Infd 0x7ff0000000000000
+#define nInfd 0xfff0000000000000
+
+#define TEST_FP_OP_H_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ la a0, test_ ## testnum ## _data ;\
+ flh f10, 0(a0); \
+ flh f11, 2(a0); \
+ flh f12, 4(a0); \
+ lh a3, 6(a0); \
+ code; \
+ fsflags a1, x0; \
+ li a2, flags; \
+ bne a0, a3, fail; \
+ bne a1, a2, fail; \
+ .pushsection .data; \
+ .align 1; \
+ test_ ## testnum ## _data: \
+ .val1; \
+ .val2; \
+ .val3; \
+ .result; \
+ .popsection
+
+#define TEST_FP_OP_S_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ la a0, test_ ## testnum ## _data ;\
+ flw f10, 0(a0); \
+ flw f11, 4(a0); \
+ flw f12, 8(a0); \
+ lw a3, 12(a0); \
+ code; \
+ fsflags a1, x0; \
+ li a2, flags; \
+ bne a0, a3, fail; \
+ bne a1, a2, fail; \
+ .pushsection .data; \
+ .align 2; \
+ test_ ## testnum ## _data: \
+ .val1; \
+ .val2; \
+ .val3; \
+ .result; \
+ .popsection
+
+#define TEST_FP_OP_D_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ la a0, test_ ## testnum ## _data ;\
+ fld f10, 0(a0); \
+ fld f11, 8(a0); \
+ fld f12, 16(a0); \
+ ld a3, 24(a0); \
+ code; \
+ fsflags a1, x0; \
+ li a2, flags; \
+ bne a0, a3, fail; \
+ bne a1, a2, fail; \
+ .pushsection .data; \
+ .align 3; \
+ test_ ## testnum ## _data: \
+ .val1; \
+ .val2; \
+ .val3; \
+ .result; \
+ .popsection
+
+// TODO: assign a separate mem location for the comparison address?
+#define TEST_FP_OP_D32_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ la a0, test_ ## testnum ## _data ;\
+ fld f10, 0(a0); \
+ fld f11, 8(a0); \
+ fld f12, 16(a0); \
+ lw a3, 24(a0); \
+ lw t1, 28(a0); \
+ code; \
+ fsflags a1, x0; \
+ li a2, flags; \
+ bne a0, a3, fail; \
+ bne t1, t2, fail; \
+ bne a1, a2, fail; \
+ .pushsection .data; \
+ .align 3; \
+ test_ ## testnum ## _data: \
+ .val1; \
+ .val2; \
+ .val3; \
+ .result; \
+ .popsection
+
+#define TEST_FCVT_S_D32( testnum, result, val1 ) \
+ TEST_FP_OP_D32_INTERNAL( testnum, 0, double result, double val1, double 0, double 0, \
+ fcvt.s.d f13, f10; fcvt.d.s f13, f13; fsd f13, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
+
+#define TEST_FCVT_S_D( testnum, result, val1 ) \
+ TEST_FP_OP_D_INTERNAL( testnum, 0, double result, double val1, double 0, double 0, \
+ fcvt.s.d f13, f10; fcvt.d.s f13, f13; fmv.x.d a0, f13)
+
+#define TEST_FCVT_D_S( testnum, result, val1 ) \
+ TEST_FP_OP_S_INTERNAL( testnum, 0, float result, float val1, float 0, float 0, \
+ fcvt.d.s f13, f10; fcvt.s.d f13, f13; fmv.x.s a0, f13)
+
+#define TEST_FCVT_H_S( testnum, result, val1 ) \
+ TEST_FP_OP_H_INTERNAL( testnum, 0, float16 result, float16 val1, float16 0, float16 0, \
+ fcvt.s.h f13, f10; fcvt.h.s f13, f13; fmv.x.h a0, f13)
+
+#define TEST_FCVT_H_D( testnum, result, val1 ) \
+ TEST_FP_OP_H_INTERNAL( testnum, 0, float16 result, float16 val1, float16 0, float16 0, \
+ fcvt.d.h f13, f10; fcvt.h.d f13, f13; fmv.x.h a0, f13)
+
+
+#define TEST_FP_OP1_H( testnum, inst, flags, result, val1 ) \
+ TEST_FP_OP_H_INTERNAL( testnum, flags, float16 result, float16 val1, float16 0, float16 0, \
+ inst f13, f10; fmv.x.h a0, f13;)
+
+#define TEST_FP_OP1_S( testnum, inst, flags, result, val1 ) \
+ TEST_FP_OP_S_INTERNAL( testnum, flags, float result, float val1, float 0, float 0, \
+ inst f13, f10; fmv.x.s a0, f13)
+
+#define TEST_FP_OP1_D32( testnum, inst, flags, result, val1 ) \
+ TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, double val1, double 0, double 0, \
+ inst f13, f10; fsd f13, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
+// ^: store computation result in address from a0, load high-word into t2
+
+#define TEST_FP_OP1_D( testnum, inst, flags, result, val1 ) \
+ TEST_FP_OP_D_INTERNAL( testnum, flags, double result, double val1, double 0, double 0, \
+ inst f13, f10; fmv.x.d a0, f13)
+
+#define TEST_FP_OP1_S_DWORD_RESULT( testnum, inst, flags, result, val1 ) \
+ TEST_FP_OP_S_INTERNAL( testnum, flags, dword result, float val1, float 0, float 0, \
+ inst f13, f10; fmv.x.s a0, f13)
+
+#define TEST_FP_OP1_H_DWORD_RESULT( testnum, inst, flags, result, val1 ) \
+ TEST_FP_OP_H_INTERNAL( testnum, flags, word result, float16 val1, float16 0, float16 0, \
+ inst f13, f10; fmv.x.h a0, f13)
+
+#define TEST_FP_OP1_D32_DWORD_RESULT( testnum, inst, flags, result, val1 ) \
+ TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, double val1, double 0, double 0, \
+ inst f13, f10; fsd f13, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
+// ^: store computation result in address from a0, load high-word into t2
+
+#define TEST_FP_OP1_D_DWORD_RESULT( testnum, inst, flags, result, val1 ) \
+ TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, double val1, double 0, double 0, \
+ inst f13, f10; fmv.x.d a0, f13)
+
+#define TEST_FP_OP2_S( testnum, inst, flags, result, val1, val2 ) \
+ TEST_FP_OP_S_INTERNAL( testnum, flags, float result, float val1, float val2, float 0, \
+ inst f13, f10, f11; fmv.x.s a0, f13)
+
+#define TEST_FP_OP2_S_HEX( testnum, inst, flags, result, val1, val2 ) \
+ TEST_FP_OP_S_INTERNAL( testnum, flags, word result, word val1, word val2, float 0, \
+ inst f13, f10, f11; fmv.x.s a0, f13)
+
+#define TEST_FP_OP2_H( testnum, inst, flags, result, val1, val2 ) \
+ TEST_FP_OP_H_INTERNAL( testnum, flags, float16 result, float16 val1, float16 val2, float16 0, \
+ inst f13, f10, f11; fmv.x.h a0, f13)
+
+#define TEST_FP_OP2_H_HEX( testnum, inst, flags, result, val1, val2 ) \
+ TEST_FP_OP_H_INTERNAL( testnum, flags, half result, half val1, half val2, float16 0, \
+ inst f13, f10, f11; fmv.x.h a0, f13)
+
+#define TEST_FP_OP2_D32( testnum, inst, flags, result, val1, val2 ) \
+ TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, double val1, double val2, double 0, \
+ inst f13, f10, f11; fsd f13, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
+// ^: store computation result in address from a0, load high-word into t2
+
+#define TEST_FP_OP2_D32_HEX( testnum, inst, flags, result, val1, val2 ) \
+ TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, dword val1, dword val2, double 0, \
+ inst f13, f10, f11; fsd f13, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
+
+#define TEST_FP_OP2_D( testnum, inst, flags, result, val1, val2 ) \
+ TEST_FP_OP_D_INTERNAL( testnum, flags, double result, double val1, double val2, double 0, \
+ inst f13, f10, f11; fmv.x.d a0, f13)
+
+#define TEST_FP_OP2_D_HEX( testnum, inst, flags, result, val1, val2 ) \
+ TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, dword val1, dword val2, double 0, \
+ inst f13, f10, f11; fmv.x.d a0, f13)
+
+#define TEST_FP_OP3_S( testnum, inst, flags, result, val1, val2, val3 ) \
+ TEST_FP_OP_S_INTERNAL( testnum, flags, float result, float val1, float val2, float val3, \
+ inst f13, f10, f11, f12; fmv.x.s a0, f13)
+
+#define TEST_FP_OP3_H( testnum, inst, flags, result, val1, val2, val3 ) \
+ TEST_FP_OP_H_INTERNAL( testnum, flags, float16 result, float16 val1, float16 val2, float16 val3, \
+ inst f13, f10, f11, f12; fmv.x.h a0, f13)
+
+#define TEST_FP_OP3_D32( testnum, inst, flags, result, val1, val2, val3 ) \
+ TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, double val1, double val2, double val3, \
+ inst f13, f10, f11, f12; fsd f13, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
+// ^: store computation result in address from a0, load high-word into t2
+
+#define TEST_FP_OP3_D( testnum, inst, flags, result, val1, val2, val3 ) \
+ TEST_FP_OP_D_INTERNAL( testnum, flags, double result, double val1, double val2, double val3, \
+ inst f13, f10, f11, f12; fmv.x.d a0, f13)
+
+#define TEST_FP_INT_OP_S( testnum, inst, flags, result, val1, rm ) \
+ TEST_FP_OP_S_INTERNAL( testnum, flags, word result, float val1, float 0, float 0, \
+ inst a0, f10, rm)
+
+#define TEST_FP_INT_OP_H( testnum, inst, flags, result, val1, rm ) \
+ TEST_FP_OP_H_INTERNAL( testnum, flags, word result, float16 val1, float16 0, float16 0, \
+ inst a0, f10, rm)
+
+#define TEST_FP_INT_OP_D32( testnum, inst, flags, result, val1, rm ) \
+ TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, double val1, double 0, double 0, \
+ inst a0, f10, rm; li t2, ((result) << 32 >> 63) * -1)
+
+#define TEST_FP_INT_OP_D( testnum, inst, flags, result, val1, rm ) \
+ TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, double val1, double 0, double 0, \
+ inst a0, f10, rm)
+
+#define TEST_FP_CMP_OP_S( testnum, inst, flags, result, val1, val2 ) \
+ TEST_FP_OP_S_INTERNAL( testnum, flags, word result, float val1, float val2, float 0, \
+ inst a0, f10, f11)
+
+#define TEST_FP_CMP_OP_S_HEX( testnum, inst, flags, result, val1, val2 ) \
+ TEST_FP_OP_S_INTERNAL( testnum, flags, word result, word val1, word val2, float 0, \
+ inst a0, f10, f11)
+
+#define TEST_FP_CMP_OP_H( testnum, inst, flags, result, val1, val2 ) \
+ TEST_FP_OP_H_INTERNAL( testnum, flags, hword result, float16 val1, float16 val2, float16 0, \
+ inst a0, f10, f11)
+
+#define TEST_FP_CMP_OP_H_HEX( testnum, inst, flags, result, val1, val2 ) \
+ TEST_FP_OP_H_INTERNAL( testnum, flags, hword result, half val1, half val2, float16 0, \
+ inst a0, f10, f11)
+
+#define TEST_FP_CMP_OP_D32( testnum, inst, flags, result, val1, val2 ) \
+ TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, double val1, double val2, double 0, \
+ inst a0, f10, f11; li t2, 0)
+
+#define TEST_FP_CMP_OP_D32_HEX( testnum, inst, flags, result, val1, val2 ) \
+ TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, dword val1, dword val2, double 0, \
+ inst a0, f10, f11; li t2, 0)
+
+#define TEST_FP_CMP_OP_D( testnum, inst, flags, result, val1, val2 ) \
+ TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, double val1, double val2, double 0, \
+ inst a0, f10, f11)
+
+#define TEST_FP_CMP_OP_D_HEX( testnum, inst, flags, result, val1, val2 ) \
+ TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, dword val1, dword val2, double 0, \
+ inst a0, f10, f11)
+
+#define TEST_FCLASS_S(testnum, correct, input) \
+ TEST_CASE(testnum, a0, correct, li a0, input; fmv.s.x f10, a0; \
+ fclass.s a0, f10)
+
+#define TEST_FCLASS_D32(testnum, correct, input) \
+ TEST_CASE(testnum, a0, correct, \
+ la a0, test_ ## testnum ## _data ;\
+ fld f10, 0(a0); \
+ fclass.d a0, f10) \
+ .pushsection .data; \
+ .align 3; \
+ test_ ## testnum ## _data: \
+ .dword input; \
+ .popsection
+
+#define TEST_FCLASS_D(testnum, correct, input) \
+ TEST_CASE(testnum, a0, correct, li a0, input; fmv.d.x f10, a0; \
+ fclass.d a0, f10)
+
+#define TEST_INT_FP_OP_S( testnum, inst, result, val1 ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ la a0, test_ ## testnum ## _data ;\
+ lw a3, 0(a0); \
+ li a0, val1; \
+ inst f10, a0; \
+ fsflags x0; \
+ fmv.x.s a0, f10; \
+ bne a0, a3, fail; \
+ .pushsection .data; \
+ .align 2; \
+ test_ ## testnum ## _data: \
+ .float result; \
+ .popsection
+
+#define TEST_INT_FP_OP_H( testnum, inst, result, val1 ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ la a0, test_ ## testnum ## _data ;\
+ lh a3, 0(a0); \
+ li a0, val1; \
+ inst f10, a0; \
+ fsflags x0; \
+ fmv.x.h a0, f10; \
+ bne a0, a3, fail; \
+ .pushsection .data; \
+ .align 1; \
+ test_ ## testnum ## _data: \
+ .float16 result; \
+ .popsection
+
+#define TEST_INT_FP_OP_D32( testnum, inst, result, val1 ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ la a0, test_ ## testnum ## _data ;\
+ lw a3, 0(a0); \
+ lw a4, 4(a0); \
+ li a1, val1; \
+ inst f10, a1; \
+ \
+ fsd f10, 0(a0); \
+ lw a1, 4(a0); \
+ lw a0, 0(a0); \
+ \
+ fsflags x0; \
+ bne a0, a3, fail; \
+ bne a1, a4, fail; \
+ .pushsection .data; \
+ .align 3; \
+ test_ ## testnum ## _data: \
+ .double result; \
+ .popsection
+
+#define TEST_INT_FP_OP_D( testnum, inst, result, val1 ) \
+test_ ## testnum: \
+ li TESTNUM, testnum; \
+ la a0, test_ ## testnum ## _data ;\
+ ld a3, 0(a0); \
+ li a0, val1; \
+ inst f10, a0; \
+ fsflags x0; \
+ fmv.x.d a0, f10; \
+ bne a0, a3, fail; \
+ .pushsection .data; \
+ .align 3; \
+ test_ ## testnum ## _data: \
+ .double result; \
+ .popsection
+
+// We need some special handling here to allow 64-bit comparison in 32-bit arch
+// TODO: find a better name and clean up when intended for general usage?
+#define TEST_CASE_D32( testnum, testreg1, testreg2, correctval, code... ) \
+test_ ## testnum: \
+ code; \
+ la x15, test_ ## testnum ## _data ; \
+ lw x7, 0(x15); \
+ lw x15, 4(x15); \
+ li TESTNUM, testnum; \
+ bne testreg1, x7, fail;\
+ bne testreg2, x15, fail;\
+ .pushsection .data; \
+ .align 3; \
+ test_ ## testnum ## _data: \
+ .dword correctval; \
+ .popsection
+
+// ^ x14 is used in some other macros, to avoid issues we use x15 for upper word
+
+#define MISALIGNED_LOAD_HANDLER \
+ li t0, CAUSE_MISALIGNED_LOAD; \
+ csrr t1, mcause; \
+ bne t0, t1, fail; \
+ \
+ /* We got a misaligned exception. Pretend we handled it in software */ \
+ /* by loading the correct result here. */ \
+ mv a4, a5; \
+ \
+ /* And skip this instruction */ \
+ csrr t0, mepc; \
+ addi t0, t0, 4; \
+ csrw mepc, t0; \
+ mret
+
+#define MISALIGNED_STORE_HANDLER \
+ li t0, CAUSE_MISALIGNED_STORE; \
+ csrr t1, mcause; \
+ bne t0, t1, fail; \
+ \
+ /* We got a misaligned exception. Skip this test. */ \
+ csrw mepc, x15; \
+ mret
+
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in TESTNUM)
+#-----------------------------------------------------------------------
+
+#define TEST_PASSFAIL \
+ bne x0, TESTNUM, pass; \
+fail: \
+ RVTEST_FAIL; \
+pass: \
+ RVTEST_PASS \
+
+
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+
+#define TEST_DATA
+
+#endif
